Searched refs:pll9 (Results 1 – 3 of 3) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| D | intel_dpll_mgr.h | 195 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; member
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| D | intel_dpll_mgr.c | 1896 temp |= pll->state.hw_state.pll9; in bxt_ddi_pll_enable()
2013 hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9)); in bxt_ddi_pll_get_hw_state()
2014 hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK; in bxt_ddi_pll_get_hw_state()
2174 dpll_hw_state->pll9 = 5 << PORT_PLL_LOCK_THRESHOLD_SHIFT; in bxt_ddi_set_dpll_hw_state()
2278 hw_state->pll9, in bxt_dump_hw_state()
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| D | intel_display.c | 14007 PIPE_CONF_CHECK_X(dpll_hw_state.pll9); in intel_pipe_config_compare()
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