Searched refs:pll_ratio (Results 1 – 9 of 9) sorted by relevance
| /drivers/phy/st/ |
| D | phy-miphy28lp.c | 240 struct pll_ratio { struct
249 static struct pll_ratio sata_pll_ratio = { argument
258 static struct pll_ratio pcie_pll_ratio = {
267 static struct pll_ratio usb3_pll_ratio = {
389 struct pll_ratio *pll_ratio) in miphy28lp_pll_calibration() argument
396 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); in miphy28lp_pll_calibration()
399 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); in miphy28lp_pll_calibration()
400 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); in miphy28lp_pll_calibration()
401 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); in miphy28lp_pll_calibration()
402 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); in miphy28lp_pll_calibration()
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| /drivers/gpu/drm/i915/display/ |
| D | vlv_dsi_pll.c | 360 u32 pll_ratio = 0; in glk_dsi_program_esc_clock() local
367 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; in glk_dsi_program_esc_clock()
369 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; in glk_dsi_program_esc_clock()
411 u32 pll_ratio = 0; in bxt_dsi_program_clocks() local
426 pll_ratio = config->dsi_pll.ctrl & BXT_DSI_PLL_RATIO_MASK; in bxt_dsi_program_clocks()
427 dsi_rate = (BXT_REF_CLOCK_KHZ * pll_ratio) / 2; in bxt_dsi_program_clocks()
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| /drivers/media/usb/dvb-usb/ |
| D | dib0700_devices.c | 225 .pll_ratio = 8,
391 .pll_ratio = 8,
660 .pll_ratio = 8,
952 .pll_ratio = 20,
1178 .pll_ratio = 20,
1517 .pll_ratio = 18,
1630 u8 pll_ratio; in dib8090_compute_pll_parameters() local
1632 for (pll_ratio = 17; pll_ratio <= 20; pll_ratio++) { in dib8090_compute_pll_parameters()
1633 freq_adc = 12 * pll_ratio * (1 << 8) / 16; in dib8090_compute_pll_parameters()
1639 deb_info("PLL ratio=%i rest=%i\n", pll_ratio, rest); in dib8090_compute_pll_parameters()
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| D | cxusb.c | 1076 .pll_ratio = 20,
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| /drivers/media/dvb-frontends/ |
| D | dibx000_common.h | 120 u8 pll_ratio; member
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| D | dib7000p.c | 453 …dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio <… in dib7000p_reset_pll()
461 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | in dib7000p_reset_pll()
467 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
500 if (loopdiv && bw && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { in dib7000p_update_pll()
501 … = %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio); in dib7000p_update_pll()
506 …dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f… in dib7000p_update_pll()
511 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */ in dib7000p_update_pll()
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| D | dib7000m.c | 401 reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset; in dib7000m_reset_pll()
414 reg_907 |= (bw->pll_ratio & 0x3f) << 9; in dib7000m_reset_pll()
431 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()
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| D | dib8000.c | 700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
730 (pll->pll_range<<12) | (pll->pll_ratio<<6) | in dib8000_reset_pll()
758 pll->pll_ratio == loopdiv)) in dib8000_update_pll()
761 … %d new = %d ; loopdiv : old = %d new = %d)\n", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio); in dib8000_update_pll()
769 ((pll->pll_ratio & 0x3f) << 6) | in dib8000_update_pll()
776 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; in dib8000_update_pll()
802 …dwidth (prediv: %d, ratio: %d)\n", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio); in dib8000_update_pll()
807 ratio = state->cfg.pll->pll_ratio; in dib8000_update_pll()
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| /drivers/media/pci/cx23885/ |
| D | cx23885-dvb.c | 1042 .pll_ratio = 20,
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