| /drivers/clk/mediatek/ |
| D | clk-pll.c | 63 u32 pcw, int postdiv) in __mtk_pll_recalc_rate() argument
86 return ((unsigned long)vco + postdiv - 1) / postdiv; in __mtk_pll_recalc_rate()
116 int postdiv) in mtk_pll_set_rate_regs() argument
126 val |= (ffs(postdiv) - 1) << pll->data->pd_shift; in mtk_pll_set_rate_regs()
159 static void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv, in mtk_pll_calc_values() argument
179 *postdiv = 1 << val; in mtk_pll_calc_values()
182 *postdiv = 1 << val; in mtk_pll_calc_values()
183 if ((u64)freq * *postdiv >= fmin) in mtk_pll_calc_values()
201 u32 postdiv; in mtk_pll_set_rate() local
203 mtk_pll_calc_values(pll, &pcw, &postdiv, rate, parent_rate); in mtk_pll_set_rate()
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| /drivers/clk/mmp/ |
| D | clk-audio.c | 119 unsigned int postdiv; in audio_pll_recalc_rate() local
138 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_recalc_rate()
144 val |= SSPA_AUD_PLL_CTRL0_DIV_OCLK_MODULO(postdivs[postdiv].modulo); in audio_pll_recalc_rate()
152 val |= SSPA_AUD_PLL_CTRL1_DIV_OCLK_PATTERN(postdivs[postdiv].pattern); in audio_pll_recalc_rate()
157 freq /= postdivs[postdiv].divisor; in audio_pll_recalc_rate()
169 unsigned int postdiv; in audio_pll_round_rate() local
175 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_round_rate()
178 freq /= postdivs[postdiv].divisor; in audio_pll_round_rate()
197 unsigned int postdiv; in audio_pll_set_rate() local
204 for (postdiv = 0; postdiv < ARRAY_SIZE(postdivs); postdiv++) { in audio_pll_set_rate()
[all …]
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| D | clk-pll.c | 49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
71 postdiv = (val >> pll->postdiv_shift) & 0x7; in mmp_clk_pll_recalc_rate()
76 do_div(rate, postdivs[postdiv]); in mmp_clk_pll_recalc_rate()
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| /drivers/clk/keystone/ |
| D | pll.c | 60 u32 postdiv; member
81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
100 postdiv = ((val & pll_data->clkod_mask) >> in clk_pllclk_recalc()
103 postdiv = readl(pll_data->pllod); in clk_pllclk_recalc()
104 postdiv = ((postdiv & pll_data->clkod_mask) >> in clk_pllclk_recalc()
107 postdiv = pll_data->postdiv; in clk_pllclk_recalc()
111 rate /= postdiv; in clk_pllclk_recalc()
172 if (of_property_read_u32(node, "fixed-postdiv", &pll_data->postdiv)) { in _of_pll_clk_init()
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| /drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_14nm.c | 680 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_recalc_rate() local
681 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_recalc_rate()
683 u8 shift = postdiv->shift; in dsi_pll_14nm_postdiv_recalc_rate()
684 u8 width = postdiv->width; in dsi_pll_14nm_postdiv_recalc_rate()
693 postdiv->flags, width); in dsi_pll_14nm_postdiv_recalc_rate()
700 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_round_rate() local
701 struct dsi_pll_14nm *pll_14nm = postdiv->pll; in dsi_pll_14nm_postdiv_round_rate()
706 postdiv->width, in dsi_pll_14nm_postdiv_round_rate()
707 postdiv->flags); in dsi_pll_14nm_postdiv_round_rate()
713 struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw); in dsi_pll_14nm_postdiv_set_rate() local
[all …]
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| /drivers/gpu/drm/bridge/ |
| D | lontium-lt9611.c | 193 … lt9611_pcr_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int postdiv) in lt9611_pcr_setup() argument
195 unsigned int pcr_m = mode->clock * 5 * postdiv / 27000; in lt9611_pcr_setup()
245 …lt9611_pll_setup(struct lt9611 *lt9611, const struct drm_display_mode *mode, unsigned int *postdiv) in lt9611_pll_setup() argument
266 *postdiv = 1; in lt9611_pll_setup()
269 *postdiv = 2; in lt9611_pll_setup()
272 *postdiv = 4; in lt9611_pll_setup()
916 unsigned int postdiv; in lt9611_bridge_mode_set() local
922 lt9611_pll_setup(lt9611, mode, &postdiv); in lt9611_bridge_mode_set()
924 lt9611_pcr_setup(lt9611, mode, postdiv); in lt9611_bridge_mode_set()
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| /drivers/clk/imx/ |
| D | clk-composite-8m.c | 52 int *prediv, int *postdiv) in imx8m_clk_composite_compute_dividers() argument
59 *postdiv = 1; in imx8m_clk_composite_compute_dividers()
67 *postdiv = div2; in imx8m_clk_composite_compute_dividers()
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| /drivers/video/fbdev/ |
| D | gxt4500.c | 238 int m, n, pdiv1, pdiv2, postdiv; in calc_pll() local
248 postdiv = pdiv1 * pdiv2; in calc_pll()
249 pll_period = DIV_ROUND_UP(period_ps, postdiv); in calc_pll()
257 n = intf * postdiv / period_ps; in calc_pll()
260 t = par->refclk_ps * m * postdiv / n; in calc_pll()
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| /drivers/clk/ |
| D | clk-axm5516.c | 52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
56 postdiv = ((control >> 0) & 0xf) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
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| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | vegam_smumgr.c | 684 table->SclkFcwRangeTable[i].postdiv = in vegam_get_sclk_range_table()
703 (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
705 (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in vegam_get_sclk_range_table()
708 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in vegam_get_sclk_range_table()
761 ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
763 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
771 ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
780 ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / in vegam_calculate_sclk_params()
782 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in vegam_calculate_sclk_params()
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| D | polaris10_smumgr.c | 812 table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv; in polaris10_get_sclk_range_table()
826 …le[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
827 …le[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
830 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv; in polaris10_get_sclk_range_table()
882 …_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
883 temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
890 …nt16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
897 …int16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); in polaris10_calculate_sclk_params()
898 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; in polaris10_calculate_sclk_params()
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| /drivers/phy/rockchip/ |
| D | phy-rockchip-inno-hdmi.c | 270 u8 postdiv; member
919 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3228_power_on()
923 int div = cfg->postdiv / 2 - 1; in inno_hdmi_phy_rk3228_power_on()
1025 if (cfg->postdiv == 1) { in inno_hdmi_phy_rk3328_power_on()
1031 v = (cfg->postdiv / 2) - 1; in inno_hdmi_phy_rk3328_power_on()
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| /drivers/media/i2c/ |
| D | ov2659.c | 897 u32 prediv, postdiv, mult; in ov2659_pll_calc_params() local
903 postdiv = ctrl1[i].div; in ov2659_pll_calc_params()
910 actual /= postdiv; in ov2659_pll_calc_params()
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| /drivers/gpu/drm/amd/pm/inc/ |
| D | smu74_discrete.h | 45 uint8_t postdiv; member
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| D | smu75_discrete.h | 44 uint8_t postdiv; /* divide by 2^n */ member
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| /drivers/gpu/drm/radeon/ |
| D | rv770_dpm.c | 342 static int rv770_encode_yclk_post_div(u32 postdiv, u32 *encoded_postdiv) in rv770_encode_yclk_post_div() argument
346 switch (postdiv) { in rv770_encode_yclk_post_div()
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