Searched refs:pp_on (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/gma500/ |
| D | cdv_intel_dp.c | 2025 u32 pp_on, pp_off, pp_div; in cdv_intel_dp_init() local
2028 pp_on = REG_READ(PP_CONTROL); in cdv_intel_dp_init()
2029 pp_on &= ~PANEL_UNLOCK_MASK; in cdv_intel_dp_init()
2030 pp_on |= PANEL_UNLOCK_REGS; in cdv_intel_dp_init()
2032 REG_WRITE(PP_CONTROL, pp_on); in cdv_intel_dp_init()
2038 pp_on = REG_READ(PP_ON_DELAYS); in cdv_intel_dp_init()
2043 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> in cdv_intel_dp_init()
2046 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> in cdv_intel_dp_init()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_dp.c | 1102 i915_reg_t pp_on; member
1122 regs->pp_on = PP_ON_DELAYS(pps_idx); in intel_pps_get_registers()
6944 u32 pp_on, pp_off, pp_ctl; in intel_pps_readout_hw_state() local
6955 pp_on = intel_de_read(dev_priv, regs.pp_on); in intel_pps_readout_hw_state()
6959 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
6960 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); in intel_pps_readout_hw_state()
7100 u32 pp_on, pp_off, port_sel = 0; in intel_dp_init_panel_power_sequencer_registers() local
7137 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | in intel_dp_init_panel_power_sequencer_registers()
7163 pp_on |= port_sel; in intel_dp_init_panel_power_sequencer_registers()
7165 intel_de_write(dev_priv, regs.pp_on, pp_on); in intel_dp_init_panel_power_sequencer_registers()
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