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Searched refs:pp_smu_wm_range_sets (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/display/dc/
Ddm_pp_smu.h88 struct pp_smu_wm_range_sets { struct
113 struct pp_smu_wm_range_sets *ranges); argument
218 struct pp_smu_wm_range_sets *ranges);
276 struct pp_smu_wm_range_sets *ranges);
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dclk_mgr.h277 struct pp_smu_wm_range_sets ranges;
/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c546 struct pp_smu_wm_range_sets *ranges) in pp_rv_set_wm_ranges()
663 struct pp_smu_wm_range_sets *ranges) in pp_nv_set_wm_ranges()
875 struct pp_smu_wm_range_sets *ranges) in pp_rn_set_wm_ranges()
/drivers/gpu/drm/amd/pm/inc/
Damdgpu_smu.h505 struct pp_smu_wm_range_sets *clock_ranges);
761 struct pp_smu_wm_range_sets *clock_ranges);
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
Drn_clk_mgr.c425 static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_smu_wm_range_sets *ra… in build_watermark_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c919 struct pp_smu_wm_range_sets *clock_ranges) in renoir_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_resource.c1480 struct pp_smu_wm_range_sets *ranges) in dummy_set_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/
Damdgpu_smu.c1831 struct pp_smu_wm_range_sets *clock_ranges) in smu_set_watermarks_for_clock_ranges()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c1550 struct pp_smu_wm_range_sets ranges = {0}; in dcn_bw_notify_pplib_of_wm_ranges()
/drivers/gpu/drm/amd/pm/swsmu/smu11/
Dnavi10_ppt.c1617 struct pp_smu_wm_range_sets *clock_ranges) in navi10_set_watermarks_table()
Dsienna_cichlid_ppt.c1448 struct pp_smu_wm_range_sets *clock_ranges) in sienna_cichlid_set_watermarks_table()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c3953 struct pp_smu_wm_range_sets ranges = {0};