| /drivers/pps/ |
| D | pps.c | 40 struct pps_device *pps = file->private_data; in pps_cdev_poll() local
42 poll_wait(file, &pps->queue, wait); in pps_cdev_poll()
49 struct pps_device *pps = file->private_data; in pps_cdev_fasync() local
50 return fasync_helper(fd, file, on, &pps->async_queue); in pps_cdev_fasync()
53 static int pps_cdev_pps_fetch(struct pps_device *pps, struct pps_fdata *fdata) in pps_cdev_pps_fetch() argument
55 unsigned int ev = pps->last_ev; in pps_cdev_pps_fetch()
60 err = wait_event_interruptible(pps->queue, in pps_cdev_pps_fetch()
61 ev != pps->last_ev); in pps_cdev_pps_fetch()
65 dev_dbg(pps->dev, "timeout %lld.%09d\n", in pps_cdev_pps_fetch()
73 pps->queue, in pps_cdev_pps_fetch()
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| D | kapi.c | 41 static void pps_echo_client_default(struct pps_device *pps, int event, in pps_echo_client_default() argument
44 dev_info(pps->dev, "echo %s %s\n", in pps_echo_client_default()
68 struct pps_device *pps; in pps_register_source() local
86 pps = kzalloc(sizeof(struct pps_device), GFP_KERNEL); in pps_register_source()
87 if (pps == NULL) { in pps_register_source()
95 pps->params.api_version = PPS_API_VERS; in pps_register_source()
96 pps->params.mode = default_params; in pps_register_source()
97 pps->info = *info; in pps_register_source()
100 if ((pps->info.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) && in pps_register_source()
101 pps->info.echo == NULL) in pps_register_source()
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| D | sysfs.c | 21 struct pps_device *pps = dev_get_drvdata(dev); in assert_show() local
23 if (!(pps->info.mode & PPS_CAPTUREASSERT)) in assert_show()
27 (long long) pps->assert_tu.sec, pps->assert_tu.nsec, in assert_show()
28 pps->assert_sequence); in assert_show()
35 struct pps_device *pps = dev_get_drvdata(dev); in clear_show() local
37 if (!(pps->info.mode & PPS_CAPTURECLEAR)) in clear_show()
41 (long long) pps->clear_tu.sec, pps->clear_tu.nsec, in clear_show()
42 pps->clear_sequence); in clear_show()
49 struct pps_device *pps = dev_get_drvdata(dev); in mode_show() local
51 return sprintf(buf, "%4x\n", pps->info.mode); in mode_show()
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| D | kc.c | 36 int pps_kc_bind(struct pps_device *pps, struct pps_bind_args *bind_args) in pps_kc_bind() argument
42 if (pps_kc_hardpps_dev == pps) { in pps_kc_bind()
46 dev_info(pps->dev, "unbound kernel" in pps_kc_bind()
50 dev_err(pps->dev, "selected kernel consumer" in pps_kc_bind()
56 pps_kc_hardpps_dev == pps) { in pps_kc_bind()
58 pps_kc_hardpps_dev = pps; in pps_kc_bind()
60 dev_info(pps->dev, "bound kernel consumer: " in pps_kc_bind()
64 dev_err(pps->dev, "another kernel consumer" in pps_kc_bind()
79 void pps_kc_remove(struct pps_device *pps) in pps_kc_remove() argument
82 if (pps == pps_kc_hardpps_dev) { in pps_kc_remove()
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| D | kc.h | 16 extern int pps_kc_bind(struct pps_device *pps,
18 extern void pps_kc_remove(struct pps_device *pps);
19 extern void pps_kc_event(struct pps_device *pps,
25 static inline int pps_kc_bind(struct pps_device *pps, in pps_kc_bind() argument
27 static inline void pps_kc_remove(struct pps_device *pps) {} in pps_kc_remove() argument
28 static inline void pps_kc_event(struct pps_device *pps, in pps_kc_event() argument
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_dsc.c | 30 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps);
203 dsc_log_pps(dsc, &dsc20->reg_vals.pps); in dsc2_set_config()
222 …drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps… in dsc2_get_packed_pps()
223 dsc_log_pps(dsc, &dsc_reg_vals.pps); in dsc2_get_packed_pps()
279 static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) in dsc_log_pps() argument
282 int bits_per_pixel = pps->bits_per_pixel; in dsc_log_pps()
284 DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); in dsc_log_pps()
285 DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); in dsc_log_pps()
286 DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); in dsc_log_pps()
287 DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); in dsc_log_pps()
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| /drivers/pps/clients/ |
| D | pps-ldisc.c | 20 struct pps_device *pps; in pps_tty_dcd_change() local
25 pps = pps_lookup_dev(tty); in pps_tty_dcd_change()
30 if (WARN_ON_ONCE(pps == NULL)) in pps_tty_dcd_change()
34 pps_event(pps, &ts, status ? PPS_CAPTUREASSERT : in pps_tty_dcd_change()
37 dev_dbg(pps->dev, "PPS %s at %lu\n", in pps_tty_dcd_change()
48 struct pps_device *pps; in pps_tty_open() local
59 pps = pps_register_source(&info, PPS_CAPTUREBOTH | \ in pps_tty_open()
61 if (IS_ERR(pps)) { in pps_tty_open()
63 return PTR_ERR(pps); in pps_tty_open()
65 pps->lookup_cookie = tty; in pps_tty_open()
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| D | pps-ktimer.c | 21 static struct pps_device *pps; variable
35 pps_event(pps, &ts, PPS_CAPTUREASSERT, NULL); in pps_ktimer_event()
59 dev_info(pps->dev, "ktimer PPS source unregistered\n"); in pps_ktimer_exit()
62 pps_unregister_source(pps); in pps_ktimer_exit()
67 pps = pps_register_source(&pps_ktimer_info, in pps_ktimer_init()
69 if (IS_ERR(pps)) { in pps_ktimer_init()
71 return PTR_ERR(pps); in pps_ktimer_init()
77 dev_info(pps->dev, "ktimer PPS source registered\n"); in pps_ktimer_init()
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| D | pps-gpio.c | 30 struct pps_device *pps; /* PPS source device */ member
59 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
63 pps_event(info->pps, &ts, PPS_CAPTURECLEAR, data); in pps_gpio_irq_handler()
69 static void pps_gpio_echo(struct pps_device *pps, int event, void *data) in pps_gpio_echo() argument
76 if (pps->params.mode & PPS_ECHOASSERT) in pps_gpio_echo()
81 if (pps->params.mode & PPS_ECHOCLEAR) in pps_gpio_echo()
87 if (info->pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) { in pps_gpio_echo()
219 data->pps = pps_register_source(&data->info, pps_default_params); in pps_gpio_probe()
220 if (IS_ERR(data->pps)) { in pps_gpio_probe()
223 return PTR_ERR(data->pps); in pps_gpio_probe()
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| D | pps_parport.c | 43 struct pps_device *pps; /* PPS device */ member
86 dev_err(dev->pps->dev, "lost the signal\n"); in parport_irq()
103 dev_err(dev->pps->dev, "disabled clear edge capture after %d" in parport_irq()
111 pps_event(dev->pps, &ts_assert, in parport_irq()
117 pps_event(dev->pps, &ts_assert, in parport_irq()
120 pps_event(dev->pps, &ts_clear, in parport_irq()
166 device->pps = pps_register_source(&info, in parport_attach()
168 if (IS_ERR(device->pps)) { in parport_attach()
204 pps_unregister_source(device->pps); in parport_detach()
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| D | Makefile | 6 obj-$(CONFIG_PPS_CLIENT_KTIMER) += pps-ktimer.o
7 obj-$(CONFIG_PPS_CLIENT_LDISC) += pps-ldisc.o
9 obj-$(CONFIG_PPS_CLIENT_GPIO) += pps-gpio.o
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| /drivers/staging/media/allegro-dvt/ |
| D | nal-h264.c | 679 static void nal_h264_rbsp_pps(struct rbsp *rbsp, struct nal_h264_pps *pps) in nal_h264_rbsp_pps() argument
683 rbsp_uev(rbsp, &pps->pic_parameter_set_id); in nal_h264_rbsp_pps()
684 rbsp_uev(rbsp, &pps->seq_parameter_set_id); in nal_h264_rbsp_pps()
685 rbsp_bit(rbsp, &pps->entropy_coding_mode_flag); in nal_h264_rbsp_pps()
686 rbsp_bit(rbsp, &pps->bottom_field_pic_order_in_frame_present_flag); in nal_h264_rbsp_pps()
687 rbsp_uev(rbsp, &pps->num_slice_groups_minus1); in nal_h264_rbsp_pps()
688 if (pps->num_slice_groups_minus1 > 0) { in nal_h264_rbsp_pps()
689 rbsp_uev(rbsp, &pps->slice_group_map_type); in nal_h264_rbsp_pps()
690 switch (pps->slice_group_map_type) { in nal_h264_rbsp_pps()
692 for (i = 0; i < pps->num_slice_groups_minus1; i++) in nal_h264_rbsp_pps()
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| D | nal-h264.h | 200 void *dest, size_t n, struct nal_h264_pps *pps);
202 struct nal_h264_pps *pps, void *src, size_t n);
203 void nal_h264_print_pps(const struct device *dev, struct nal_h264_pps *pps);
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| /drivers/gpu/drm/i915/display/ |
| D | intel_lvds.c | 154 struct intel_lvds_pps *pps) in intel_lvds_pps_get_hw_state() argument
158 pps->powerdown_on_reset = intel_de_read(dev_priv, PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
161 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
162 pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
163 pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
166 pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
170 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
180 pps->t4 = val * 1000; in intel_lvds_pps_get_hw_state()
183 pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { in intel_lvds_pps_get_hw_state()
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| /drivers/staging/media/hantro/ |
| D | hantro_g1_h264_dec.c | 27 const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; in set_params() local
59 reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | in set_params()
60 G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset); in set_params()
62 if (pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) in set_params()
70 G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) | in set_params()
77 G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc); in set_params()
78 if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) in set_params()
84 if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) in set_params()
91 if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) in set_params()
93 if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) in set_params()
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| D | hantro_h264.c | 200 const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; in assemble_scaling_list() local
209 if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)) in assemble_scaling_list()
361 ctrls->pps = in hantro_h264_dec_prepare_run()
363 if (WARN_ON(!ctrls->pps)) in hantro_h264_dec_prepare_run()
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| /drivers/gpu/drm/amd/display/dc/dsc/ |
| D | rc_calc.c | 319 void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) in calc_rc_params() argument
324 u16 drm_bpp = pps->bits_per_pixel; in calc_rc_params()
325 int slice_width = pps->slice_width; in calc_rc_params()
326 int slice_height = pps->slice_height; in calc_rc_params()
328 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : in calc_rc_params()
329 (pps->native_422 ? CM_422 : in calc_rc_params()
330 pps->native_420 ? CM_420 : CM_444)); in calc_rc_params()
331 bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) in calc_rc_params()
334 is_navite_422_or_420 = pps->native_422 || pps->native_420; in calc_rc_params()
339 pps->dsc_version_minor); in calc_rc_params()
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| D | rc_calc_dpi.c | 99 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params) in dscc_compute_dsc_parameters() argument
105 dsc_params->bytes_per_pixel = calc_dsc_bytes_per_pixel(pps); in dscc_compute_dsc_parameters()
107 calc_rc_params(&rc, pps); in dscc_compute_dsc_parameters()
108 dsc_params->pps = *pps; in dscc_compute_dsc_parameters()
109 …dsc_params->pps.initial_scale_value = 8 * rc.rc_model_size / (rc.rc_model_size - rc.initial_fullne… in dscc_compute_dsc_parameters()
111 copy_pps_fields(&dsc_cfg, &dsc_params->pps); in dscc_compute_dsc_parameters()
114 dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64; in dscc_compute_dsc_parameters()
118 copy_pps_fields(&dsc_params->pps, &dsc_cfg); in dscc_compute_dsc_parameters()
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| D | dscc_types.h | 42 struct drm_dsc_config pps; member
49 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params…
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| D | rc_calc.h | 80 void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps);
81 u32 calc_dsc_bytes_per_pixel(const struct drm_dsc_config *pps);
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| /drivers/staging/media/sunxi/cedrus/ |
| D | cedrus_h265.c | 249 const struct v4l2_ctrl_hevc_pps *pps; in cedrus_h265_setup() local
260 pps = run->h265.pps; in cedrus_h265_setup()
397 reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) | in cedrus_h265_setup()
398 VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) | in cedrus_h265_setup()
399 VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) | in cedrus_h265_setup()
400 VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth); in cedrus_h265_setup()
404 pps->flags); in cedrus_h265_setup()
408 pps->flags); in cedrus_h265_setup()
412 pps->flags); in cedrus_h265_setup()
416 pps->flags); in cedrus_h265_setup()
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| D | cedrus_h264.c | 241 const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; in cedrus_write_scaling_lists() local
244 if (!(pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT)) in cedrus_write_scaling_lists()
326 const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; in cedrus_set_params() local
371 if (V4L2_H264_CTRL_PRED_WEIGHTS_REQUIRED(pps, slice)) in cedrus_set_params()
390 reg |= (pps->weighted_bipred_idc & 0x3) << 2; in cedrus_set_params()
391 if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) in cedrus_set_params()
393 if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) in cedrus_set_params()
395 if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) in cedrus_set_params()
397 if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) in cedrus_set_params()
446 reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; in cedrus_set_params()
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| /drivers/staging/media/rkvdec/ |
| D | rkvdec-h264.c | 113 const struct v4l2_ctrl_h264_pps *pps; member
641 const struct v4l2_ctrl_h264_pps *pps = run->pps; in assemble_hw_pps() local
656 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
687 WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), in assemble_hw_pps()
689 WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), in assemble_hw_pps()
691 WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1, in assemble_hw_pps()
693 WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1, in assemble_hw_pps()
695 WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED), in assemble_hw_pps()
697 WRITE_PPS(pps->weighted_bipred_idc, WEIGHTED_BIPRED_IDC); in assemble_hw_pps()
698 WRITE_PPS(pps->pic_init_qp_minus26, PIC_INIT_QP_MINUS26); in assemble_hw_pps()
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| /drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_vbif.c | 73 u64 pps; in _dpu_vbif_apply_dynamic_ot_limit() local
84 pps = params->frame_rate; in _dpu_vbif_apply_dynamic_ot_limit()
85 pps *= params->width; in _dpu_vbif_apply_dynamic_ot_limit()
86 pps *= params->height; in _dpu_vbif_apply_dynamic_ot_limit()
92 if (pps <= tbl->cfg[i].pps) { in _dpu_vbif_apply_dynamic_ot_limit()
101 pps, *ot_lim); in _dpu_vbif_apply_dynamic_ot_limit()
324 (u64 *)&cfg->pps); in dpu_debugfs_vbif_init()
338 (u64 *)&cfg->pps); in dpu_debugfs_vbif_init()
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| /drivers/ptp/ |
| D | ptp_clock.c | 250 if (info->pps) { in ptp_clock_register()
251 struct pps_source_info pps; in ptp_clock_register() local
252 memset(&pps, 0, sizeof(pps)); in ptp_clock_register()
253 snprintf(pps.name, PPS_MAX_NAME_LEN, "ptp%d", index); in ptp_clock_register()
254 pps.mode = PTP_PPS_MODE; in ptp_clock_register()
255 pps.owner = info->owner; in ptp_clock_register()
256 ptp->pps_source = pps_register_source(&pps, PTP_PPS_DEFAULTS); in ptp_clock_register()
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