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Searched refs:rFPGA0_RFMOD (Results 1 – 13 of 13) sorted by relevance

/drivers/staging/rtl8712/
Drtl871x_mp.c349 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x0); in r8712_SwitchBandwidth()
359 set_bb_reg(pAdapter, rFPGA0_RFMOD, bRFMOD, 0x1); in r8712_SwitchBandwidth()
503 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn)) in r8712_SetSingleCarrierTx()
505 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); in r8712_SetSingleCarrierTx()
541 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bDisable); in r8712_SetSingleToneTx()
542 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bDisable); in r8712_SetSingleToneTx()
550 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, bEnable); in r8712_SetSingleToneTx()
551 set_bb_reg(pAdapter, rFPGA0_RFMOD, bOFDMEn, bEnable); in r8712_SetSingleToneTx()
566 if (!get_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn)) { in r8712_SetCarrierSuppressionTx()
568 set_bb_reg(pAdapter, rFPGA0_RFMOD, bCCKEn, in r8712_SetCarrierSuppressionTx()
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Drtl871x_mp_phy_regdef.h85 #define rFPGA0_RFMOD 0x800 /*RF mode & CCK TxSC RF macro
/drivers/staging/rtl8192u/
Dr819xU_phyreg.h8 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
Dr819xU_phy.c784 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in rtl8192_BB_Config_ParaFile()
1475 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in rtl8192_SetBWModeWorkItem()
1505 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in rtl8192_SetBWModeWorkItem()
Dr8192U_core.c2791 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl8192_adapter_start()
2792 rtl8192_setBBreg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl8192_adapter_start()
/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h20 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting */ macro
/drivers/staging/rtl8188eu/hal/
Dphy.c228 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_set_bw_mode_callback()
232 phy_set_bb_reg(adapt, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_set_bw_mode_callback()
974 rFPGA0_XB_RFInterfaceOE, rFPGA0_RFMOD in phy_iq_calibrate()
1005 phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00); in phy_iq_calibrate()
Dusb_halinit.c588 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bCCKEn, 0x1); in _BBTurnOnBlock()
589 phy_set_bb_reg(Adapter, rFPGA0_RFMOD, bOFDMEn, 0x1); in _BBTurnOnBlock()
/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c788 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0); in phy_PostSetBwMode8723B()
799 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1); in phy_PostSetBwMode8723B()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phy.c552 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0); in _rtl92e_bb_config_para_file()
1192 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x0); in _rtl92e_set_bw_mode_work_item()
1207 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bRFMOD, 0x1); in _rtl92e_set_bw_mode_work_item()
Dr8192E_phyreg.h47 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ macro
Dr8192E_dev.c854 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bCCKEn, 0x1); in rtl92e_start_adapter()
855 rtl92e_set_bb_reg(dev, rFPGA0_RFMOD, bOFDMEn, 0x1); in rtl92e_start_adapter()
/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h92 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC RF BW Setting?? */ macro