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Searched refs:rFPGA0_XA_LSSIParameter (Results 1 – 10 of 10) sorted by relevance

/drivers/staging/rtl8192u/
Dr819xU_phyreg.h18 #define rFPGA0_XA_LSSIParameter 0x840 macro
Dr819xU_phy.c588 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; in rtl8192_InitBBRFRegDef()
/drivers/staging/rtl8188eu/include/
Dhal8188e_phy_reg.h28 #define rFPGA0_XA_LSSIParameter 0x840 macro
/drivers/staging/rtl8188eu/hal/
Dbb_cfg.c596 reg[RF_PATH_A]->rf3wireOffset = rFPGA0_XA_LSSIParameter; in rtl88e_phy_init_bb_rf_register_definition()
Dphy.c1016 phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord, in phy_iq_calibrate()
1122 phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, in phy_iq_calibrate()
/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h61 #define rFPGA0_XA_LSSIParameter 0x840 macro
Dr8192E_phy.c402 priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; in _rtl92e_init_bb_rf_reg_def()
/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h101 #define rFPGA0_XA_LSSIParameter 0x840 macro
/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h114 #define rFPGA0_XA_LSSIParameter 0x840 macro
/drivers/staging/rtl8723bs/hal/
Drtl8723b_phycfg.c399 pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */ in phy_InitBBRFRegisterDefinition()