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Searched refs:ratios (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c180 if (data->ratios.horz.value == one in dpp1_dscl_get_dscl_mode()
181 && data->ratios.vert.value == one in dpp1_dscl_get_dscl_mode()
182 && data->ratios.horz_c.value == one in dpp1_dscl_get_dscl_mode()
183 && data->ratios.vert_c.value == one in dpp1_dscl_get_dscl_mode()
193 if (data->ratios.horz.value == one && data->ratios.vert.value == one) in dpp1_dscl_get_dscl_mode()
195 if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) in dpp1_dscl_get_dscl_mode()
335 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
337 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
344 scl_data->taps.h_taps_c, scl_data->ratios.horz_c); in dpp1_dscl_set_scl_filter()
346 scl_data->taps.v_taps_c, scl_data->ratios.vert_c); in dpp1_dscl_set_scl_filter()
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Ddcn10_dpp.c140 scl_data->ratios.horz.value != dc_fixpt_one.value && in dpp1_get_optimal_number_of_taps()
141 scl_data->ratios.vert.value != dc_fixpt_one.value) in dpp1_get_optimal_number_of_taps()
152 if (scl_data->ratios.horz.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
153 scl_data->ratios.horz.value--; in dpp1_get_optimal_number_of_taps()
154 if (scl_data->ratios.vert.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
155 scl_data->ratios.vert.value--; in dpp1_get_optimal_number_of_taps()
156 if (scl_data->ratios.horz_c.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
157 scl_data->ratios.horz_c.value--; in dpp1_get_optimal_number_of_taps()
158 if (scl_data->ratios.vert_c.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
159 scl_data->ratios.vert_c.value--; in dpp1_get_optimal_number_of_taps()
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Ddcn10_hw_sequencer.c3390 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dcn10_set_cursor_position()
3391 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn10_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c286 dc_fixpt_u2d19(data->ratios.horz) << 5; in calculate_inits()
288 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
293 data->ratios.horz, in calculate_inits()
302 data->ratios.vert, in calculate_inits()
318 dc_fixpt_u2d19(data->ratios.horz) << 5; in dce60_calculate_inits()
320 dc_fixpt_u2d19(data->ratios.vert) << 5; in dce60_calculate_inits()
331 data->ratios.vert, in dce60_calculate_inits()
439 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce_transform_set_scaler()
440 coeffs_h = get_filter_coeffs_16p(data->taps.h_taps, data->ratios.horz); in dce_transform_set_scaler()
525 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce60_transform_set_scaler()
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/drivers/clk/mvebu/
Dorion.c80 .ratios = orion_coreclk_ratios,
148 .ratios = orion_coreclk_ratios,
205 .ratios = orion_coreclk_ratios,
268 .ratios = orion_coreclk_ratios,
Dkirkwood.c197 .ratios = kirkwood_coreclk_ratios,
205 .ratios = kirkwood_coreclk_ratios,
213 .ratios = kirkwood_coreclk_ratios,
Dcommon.h34 const struct coreclk_ratio *ratios; member
Dcommon.c157 const char *rclk_name = desc->ratios[n].name; in mvebu_coreclk_setup()
162 desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div); in mvebu_coreclk_setup()
Darmada-39x.c123 .ratios = armada_39x_coreclk_ratios,
Darmada-375.c136 .ratios = armada_375_coreclk_ratios,
Darmada-38x.c120 .ratios = armada_38x_coreclk_ratios,
Dmv98dx3236.c149 .ratios = mv98dx3236_core_ratios,
Ddove.c152 .ratios = dove_coreclk_ratios,
Darmada-xp.c155 .ratios = axp_coreclk_ratios,
Darmada-370.c146 .ratios = a370_coreclk_ratios,
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c406 if (dc_fixpt_ceil(scl_data->ratios.horz) > 1) in dpp3_get_optimal_number_of_taps()
407 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
413 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) in dpp3_get_optimal_number_of_taps()
414 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
420 if (dc_fixpt_ceil(scl_data->ratios.vert_c) > 1) in dpp3_get_optimal_number_of_taps()
421 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8); in dpp3_get_optimal_number_of_taps()
427 if (dc_fixpt_ceil(scl_data->ratios.horz_c) > 1) in dpp3_get_optimal_number_of_taps()
428 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); in dpp3_get_optimal_number_of_taps()
438 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); in dpp3_get_optimal_number_of_taps()
439 min_taps_c = dc_fixpt_ceil(scl_data->ratios.vert_c); in dpp3_get_optimal_number_of_taps()
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/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c850 pipe_ctx->plane_res.scl_data.ratios.horz = dc_fixpt_from_fraction( in calculate_scaling_ratios()
853 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
858 pipe_ctx->plane_res.scl_data.ratios.horz.value *= 2; in calculate_scaling_ratios()
860 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
862 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
863 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
864 pipe_ctx->plane_res.scl_data.ratios.horz.value = div64_s64( in calculate_scaling_ratios()
865 pipe_ctx->plane_res.scl_data.ratios.horz.value * in_w, out_w); in calculate_scaling_ratios()
867 pipe_ctx->plane_res.scl_data.ratios.horz_c = pipe_ctx->plane_res.scl_data.ratios.horz; in calculate_scaling_ratios()
868 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
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/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_transform_v.c378 dc_fixpt_u2d19(data->ratios.horz) << 5; in calculate_inits()
380 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
382 dc_fixpt_u2d19(data->ratios.horz_c) << 5; in calculate_inits()
384 dc_fixpt_u2d19(data->ratios.vert_c) << 5; in calculate_inits()
562 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
563 coeffs_h = get_filter_coeffs_64p(data->taps.h_taps, data->ratios.horz); in dce110_xfmv_set_scaler()
564 coeffs_v_c = get_filter_coeffs_64p(data->taps.v_taps_c, data->ratios.vert_c); in dce110_xfmv_set_scaler()
565 coeffs_h_c = get_filter_coeffs_64p(data->taps.h_taps_c, data->ratios.horz_c); in dce110_xfmv_set_scaler()
Ddce110_hw_sequencer.c2754 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, in dce110_set_cursor_position()
2755 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dce110_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c399 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
407 input->scale_ratio_depth.hscl_ratio_c = pipe->plane_res.scl_data.ratios.horz_c.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
408 input->scale_ratio_depth.vscl_ratio_c = pipe->plane_res.scl_data.ratios.vert_c.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
995 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value in dcn_validate_bandwidth()
997 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()
1000 ASSERT(pipe->plane_res.scl_data.ratios.horz.value != dc_fixpt_one.value in dcn_validate_bandwidth()
1002 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()
Ddce_calcs.c2804 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2805 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
2860 pipe[i].bottom_pipe->plane_res.scl_data.ratios.horz.value); in populate_initial_data()
2862 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); in populate_initial_data()
2906 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2907 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtransform.h179 struct scaling_ratios ratios; member
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c1903 sd->ratios.horz, sd->recout.width - new_width)); in dcn20_split_stream_for_odm()
1905 sd->ratios.horz_c, sd->recout.width - new_width)); in dcn20_split_stream_for_odm()
1917 sd->ratios.horz, sd->recout.width - new_width)); in dcn20_split_stream_for_odm()
1919 sd->ratios.horz_c, sd->recout.width - new_width)); in dcn20_split_stream_for_odm()
1922 sd->ratios.horz, sd->h_active - sd->recout.x)); in dcn20_split_stream_for_odm()
1924 sd->ratios.horz_c, sd->h_active - sd->recout.x)); in dcn20_split_stream_for_odm()
2334 pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2335 …pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<3…
2336 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2337 …pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<3…
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