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Searched refs:rd_regl (Results 1 – 5 of 5) sorted by relevance

/drivers/tty/serial/
Dsirfsoc_uart.c72 reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status); in sirfsoc_uart_tx_empty()
83 if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) & in sirfsoc_uart_get_mctrl()
111 rd_regl(port, ureg->sirfsoc_line_ctrl) | in sirfsoc_uart_set_mctrl()
115 rd_regl(port, ureg->sirfsoc_mode1) | in sirfsoc_uart_set_mctrl()
120 rd_regl(port, ureg->sirfsoc_line_ctrl) & in sirfsoc_uart_set_mctrl()
124 rd_regl(port, ureg->sirfsoc_mode1) & in sirfsoc_uart_set_mctrl()
131 current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF; in sirfsoc_uart_set_mctrl()
155 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
163 wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port, in sirfsoc_uart_stop_tx()
167 rd_regl(port, ureg->sirfsoc_int_en_reg) & in sirfsoc_uart_stop_tx()
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Dsamsung_tty.c170 #define rd_regl(port, reg) (readl_relaxed(portaddr(port, reg))) macro
195 val = rd_regl(port, reg); in s3c24xx_set_bit()
208 val = rd_regl(port, reg); in s3c24xx_clear_bit()
228 return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE; in s3c24xx_serial_txempty_nofifo()
253 ufcon = rd_regl(port, S3C2410_UFCON); in s3c24xx_serial_rx_enable()
257 ucon = rd_regl(port, S3C2410_UCON); in s3c24xx_serial_rx_enable()
273 ucon = rd_regl(port, S3C2410_UCON); in s3c24xx_serial_rx_disable()
362 ucon = rd_regl(port, S3C2410_UCON); in enable_tx_dma()
378 ufcon = rd_regl(port, S3C2410_UFCON); in enable_tx_pio()
382 ucon = rd_regl(port, S3C2410_UCON); in enable_tx_pio()
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Dsirfsoc_uart.h441 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg))) macro
/drivers/atm/
Dhorizon.h478 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | GREEN_LED)
480 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ GREEN_LED)
482 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) | YELLOW_LED)
484 wr_regl (dev, CONTROL_0_REG, rd_regl (dev, CONTROL_0_REG) &~ YELLOW_LED)
Dhorizon.c360 static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) { in rd_regl() function
392 return rd_regl (dev, MEMORY_PORT_OFF); in rd_mem()
402 return rd_regl (dev, MEMORY_PORT_OFF); in rd_framer()
467 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG)); in dump_regs()
471 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF)); in dump_regs()
472 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF)); in dump_regs()
932 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) { in rx_schedule()
1098 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) { in tx_schedule()
1358 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF) in interrupt_handler()
1721 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG); in hrz_reset()
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