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Searched refs:reg_idx (Results 1 – 25 of 72) sorted by relevance

123

/drivers/net/ethernet/intel/ixgbe/
Dixgbe_lib.c24 u16 reg_idx, pool; in ixgbe_cache_ring_dcb_sriov() local
36 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
37 for (i = 0, pool = 0; i < adapter->num_rx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
39 if ((reg_idx & ~vmdq->mask) >= tcs) { in ixgbe_cache_ring_dcb_sriov()
41 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
43 adapter->rx_ring[i]->reg_idx = reg_idx; in ixgbe_cache_ring_dcb_sriov()
47 reg_idx = vmdq->offset * __ALIGN_MASK(1, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
48 for (i = 0; i < adapter->num_tx_queues; i++, reg_idx++) { in ixgbe_cache_ring_dcb_sriov()
50 if ((reg_idx & ~vmdq->mask) >= tcs) in ixgbe_cache_ring_dcb_sriov()
51 reg_idx = __ALIGN_MASK(reg_idx, ~vmdq->mask); in ixgbe_cache_ring_dcb_sriov()
[all …]
Dixgbe_main.c1226 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1227 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)), in ixgbe_clean_tx_irq()
1285 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1289 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx); in ixgbe_update_tx_dca()
1315 u8 reg_idx = rx_ring->reg_idx; in ixgbe_update_rx_dca() local
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl); in ixgbe_update_rx_dca()
2480 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbe_configure_msix()
2483 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbe_configure_msix()
3476 u8 reg_idx = ring->reg_idx; in ixgbe_configure_tx_ring() local
3483 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0); in ixgbe_configure_tx_ring()
[all …]
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_interrupts.c189 u32 reg_idx; member
777 int reg_idx; in dpu_hw_intr_dispatch_irq() local
793 for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) { in dpu_hw_intr_dispatch_irq()
794 irq_status = intr->save_irq_status[reg_idx]; in dpu_hw_intr_dispatch_irq()
800 start_idx = reg_idx * 32; in dpu_hw_intr_dispatch_irq()
803 if (!test_bit(reg_idx, &intr->irq_mask) || in dpu_hw_intr_dispatch_irq()
816 (dpu_irq_map[irq_idx].reg_idx == reg_idx)) { in dpu_hw_intr_dispatch_irq()
843 int reg_idx; in dpu_hw_intr_enable_irq() local
859 reg_idx = irq->reg_idx; in dpu_hw_intr_enable_irq()
860 reg = &dpu_intr_set[reg_idx]; in dpu_hw_intr_enable_irq()
[all …]
/drivers/staging/media/atomisp/pci/css_2401_system/host/
Disys_irq_private.h70 const unsigned int reg_idx, in isys_irqc_reg_store() argument
76 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); in isys_irqc_reg_store()
78 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_store()
87 const unsigned int reg_idx) in isys_irqc_reg_load() argument
93 assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); in isys_irqc_reg_load()
95 reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); in isys_irqc_reg_load()
Disys_stream2mmio_private.h139 const uint32_t reg_idx) in stream2mmio_reg_load() argument
147 (reg_bank_offset + reg_idx) * sizeof(hrt_data)); in stream2mmio_reg_load()
/drivers/soc/renesas/
Dr8a779a0-sysc.c170 static int clear_irq_flags(unsigned int reg_idx, unsigned int isr_mask) in clear_irq_flags() argument
175 iowrite32(isr_mask, r8a779a0_sysc_base + SYSCISCR(reg_idx)); in clear_irq_flags()
177 ret = readl_poll_timeout_atomic(r8a779a0_sysc_base + SYSCISCR(reg_idx), in clear_irq_flags()
191 unsigned int reg_idx, bit_idx; in r8a779a0_sysc_power() local
200 reg_idx = pdr / NUM_DOMAINS_EACH_REG; in r8a779a0_sysc_power()
209 iowrite32(ioread32(r8a779a0_sysc_base + SYSCIER(reg_idx)) | isr_mask, in r8a779a0_sysc_power()
210 r8a779a0_sysc_base + SYSCIER(reg_idx)); in r8a779a0_sysc_power()
211 iowrite32(ioread32(r8a779a0_sysc_base + SYSCIMR(reg_idx)) | isr_mask, in r8a779a0_sysc_power()
212 r8a779a0_sysc_base + SYSCIMR(reg_idx)); in r8a779a0_sysc_power()
214 ret = clear_irq_flags(reg_idx, isr_mask); in r8a779a0_sysc_power()
[all …]
/drivers/i2c/
Di2c-slave-testunit.c40 u8 reg_idx; member
98 if (tu->reg_idx < TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
99 tu->regs[tu->reg_idx] = *val; in i2c_slave_testunit_slave_cb()
103 if (tu->reg_idx <= TU_NUM_REGS) in i2c_slave_testunit_slave_cb()
104 tu->reg_idx++; in i2c_slave_testunit_slave_cb()
113 if (tu->reg_idx == TU_NUM_REGS) { in i2c_slave_testunit_slave_cb()
121 tu->reg_idx = 0; in i2c_slave_testunit_slave_cb()
/drivers/irqchip/
Dirq-mvebu-sei.c59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq() local
62 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq() local
73 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
75 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
82 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq() local
87 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
89 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
359 u32 reg_idx; in mvebu_sei_reset() local
362 for (reg_idx = 0; reg_idx < SEI_IRQ_REG_COUNT; reg_idx++) { in mvebu_sei_reset()
[all …]
Dirq-pruss-intc.c181 u8 ch, host, reg_idx; in pruss_intc_map() local
193 reg_idx = hwirq / 32; in pruss_intc_map()
197 pruss_intc_write_reg(intc, PRU_INTC_ESR(reg_idx), val); in pruss_intc_map()
198 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_map()
224 u8 ch, host, reg_idx; in pruss_intc_unmap() local
241 reg_idx = hwirq / 32; in pruss_intc_unmap()
245 pruss_intc_write_reg(intc, PRU_INTC_ECR(reg_idx), val); in pruss_intc_unmap()
247 pruss_intc_write_reg(intc, PRU_INTC_SECR(reg_idx), val); in pruss_intc_unmap()
/drivers/misc/habanalabs/goya/
Dgoya_coresight.c238 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in goya_config_stm()
243 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in goya_config_stm()
311 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in goya_config_etf()
316 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in goya_config_etf()
479 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in goya_config_funnel()
484 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in goya_config_funnel()
500 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in goya_config_bmon()
505 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in goya_config_bmon()
529 if (params->reg_idx != GOYA_BMON_PCIE_MSTR_RD && in goya_config_bmon()
530 params->reg_idx != GOYA_BMON_PCIE_MSTR_WR && in goya_config_bmon()
[all …]
/drivers/sh/intc/
Dhandle.c41 unsigned int *reg_idx, in _intc_mask_data() argument
48 while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) { in _intc_mask_data()
49 mr = desc->hw.mask_regs + *reg_idx; in _intc_mask_data()
82 (*reg_idx)++; in _intc_mask_data()
109 unsigned int *reg_idx, in _intc_prio_data() argument
116 while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) { in _intc_prio_data()
117 pr = desc->hw.prio_regs + *reg_idx; in _intc_prio_data()
151 (*reg_idx)++; in _intc_prio_data()
/drivers/net/ethernet/intel/fm10k/
Dfm10k_pci.c876 u8 reg_idx = ring->reg_idx; in fm10k_configure_tx_ring() local
879 fm10k_write_reg(hw, FM10K_TXDCTL(reg_idx), 0); in fm10k_configure_tx_ring()
885 fm10k_write_reg(hw, FM10K_TDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in fm10k_configure_tx_ring()
886 fm10k_write_reg(hw, FM10K_TDBAH(reg_idx), tdba >> 32); in fm10k_configure_tx_ring()
887 fm10k_write_reg(hw, FM10K_TDLEN(reg_idx), size); in fm10k_configure_tx_ring()
890 fm10k_write_reg(hw, FM10K_TDH(reg_idx), 0); in fm10k_configure_tx_ring()
891 fm10k_write_reg(hw, FM10K_TDT(reg_idx), 0); in fm10k_configure_tx_ring()
894 ring->tail = &interface->uc_addr[FM10K_TDT(reg_idx)]; in fm10k_configure_tx_ring()
906 fm10k_write_reg(hw, FM10K_TXINT(reg_idx), txint); in fm10k_configure_tx_ring()
909 fm10k_write_reg(hw, FM10K_PFVTCTL(reg_idx), in fm10k_configure_tx_ring()
[all …]
/drivers/media/platform/mtk-vcodec/
Dmtk_vcodec_util.c24 unsigned int reg_idx) in mtk_vcodec_get_reg_addr() argument
28 if (!data || reg_idx >= NUM_MAX_VCODEC_REG_BASE) { in mtk_vcodec_get_reg_addr()
29 mtk_v4l2_err("Invalid arguments, reg_idx=%d", reg_idx); in mtk_vcodec_get_reg_addr()
32 return ctx->dev->reg_base[reg_idx]; in mtk_vcodec_get_reg_addr()
/drivers/net/ethernet/intel/ixgbevf/
Dixgbevf_main.c200 u32 head = IXGBE_READ_REG(hw, IXGBE_VFTDH(ring->reg_idx)); in ixgbevf_get_tx_pending()
201 u32 tail = IXGBE_READ_REG(hw, IXGBE_VFTDT(ring->reg_idx)); in ixgbevf_get_tx_pending()
385 IXGBE_READ_REG(hw, IXGBE_VFTDH(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
386 IXGBE_READ_REG(hw, IXGBE_VFTDT(tx_ring->reg_idx)), in ixgbevf_clean_tx_irq()
1373 ixgbevf_set_ivar(adapter, 0, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1376 ixgbevf_set_ivar(adapter, 1, ring->reg_idx, v_idx); in ixgbevf_configure_msix()
1699 u8 reg_idx = ring->reg_idx; in ixgbevf_configure_tx_ring() local
1702 IXGBE_WRITE_REG(hw, IXGBE_VFTXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH); in ixgbevf_configure_tx_ring()
1705 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAL(reg_idx), tdba & DMA_BIT_MASK(32)); in ixgbevf_configure_tx_ring()
1706 IXGBE_WRITE_REG(hw, IXGBE_VFTDBAH(reg_idx), tdba >> 32); in ixgbevf_configure_tx_ring()
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/drivers/bus/
Dimx-weim.c136 int reg_idx, num_regs; in weim_timing_setup() local
158 for (reg_idx = 0; reg_idx < num_regs; reg_idx++) { in weim_timing_setup()
161 reg_idx * OF_REG_SIZE, &cs_idx); in weim_timing_setup()
/drivers/misc/habanalabs/gaudi/
Dgaudi_coresight.c399 if (params->reg_idx >= ARRAY_SIZE(debug_stm_regs)) { in gaudi_config_stm()
404 base_reg = debug_stm_regs[params->reg_idx] - CFG_BASE; in gaudi_config_stm()
477 if (params->reg_idx >= ARRAY_SIZE(debug_etf_regs)) { in gaudi_config_etf()
482 base_reg = debug_etf_regs[params->reg_idx] - CFG_BASE; in gaudi_config_etf()
685 if (params->reg_idx >= ARRAY_SIZE(debug_funnel_regs)) { in gaudi_config_funnel()
690 base_reg = debug_funnel_regs[params->reg_idx] - CFG_BASE; in gaudi_config_funnel()
705 if (params->reg_idx >= ARRAY_SIZE(debug_bmon_regs)) { in gaudi_config_bmon()
710 base_reg = debug_bmon_regs[params->reg_idx] - CFG_BASE; in gaudi_config_bmon()
773 if (params->reg_idx >= ARRAY_SIZE(debug_spmu_regs)) { in gaudi_config_spmu()
778 base_reg = debug_spmu_regs[params->reg_idx] - CFG_BASE; in gaudi_config_spmu()
[all …]
/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
Disys_irq_public.h31 const unsigned int reg_idx,
35 const unsigned int reg_idx);
/drivers/net/ethernet/intel/ice/
Dice_xsk.c84 reg = rx_ring->reg_idx; in ice_qvec_dis_irq()
92 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), 0); in ice_qvec_dis_irq()
106 u16 reg_idx = q_vector->reg_idx; in ice_qvec_cfg_msix() local
113 wr32(hw, GLINT_RATE(reg_idx), in ice_qvec_cfg_msix()
117 ice_cfg_txq_interrupt(vsi, ring->reg_idx, reg_idx, in ice_qvec_cfg_msix()
121 ice_cfg_rxq_interrupt(vsi, ring->reg_idx, reg_idx, in ice_qvec_cfg_msix()
Dice_base.c648 pf_q = ring->reg_idx; in ice_vsi_cfg_txq()
707 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), in ice_cfg_itr()
717 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx), in ice_cfg_itr()
788 wr32(hw, GLINT_DYN_CTL(q_vector->reg_idx), in ice_trigger_sw_intr()
814 val = rd32(hw, QINT_TQCTL(ring->reg_idx)); in ice_vsi_stop_tx_ring()
816 wr32(hw, QINT_TQCTL(ring->reg_idx), val); in ice_vsi_stop_tx_ring()
871 txq_meta->q_id = ring->reg_idx; in ice_fill_txq_meta()
Dice_lib.c1262 ring->reg_idx = vsi->txq_map[i]; in ice_vsi_alloc_rings()
1281 ring->reg_idx = vsi->rxq_map[i]; in ice_vsi_alloc_rings()
1809 u16 reg_idx = q_vector->reg_idx; in ice_vsi_cfg_msix() local
1813 wr32(hw, GLINT_RATE(reg_idx), in ice_vsi_cfg_msix()
1828 ice_cfg_txq_interrupt(vsi, txq, reg_idx, in ice_vsi_cfg_msix()
1834 ice_cfg_rxq_interrupt(vsi, rxq, reg_idx, in ice_vsi_cfg_msix()
2120 q_vector->reg_idx = ice_calc_vf_reg_idx(vf, q_vector); in ice_vsi_set_q_vectors_reg_idx()
2122 q_vector->reg_idx = in ice_vsi_set_q_vectors_reg_idx()
2134 q_vector->reg_idx = 0; in ice_vsi_set_q_vectors_reg_idx()
2373 u16 reg_idx = q_vector->reg_idx; in ice_vsi_release_msix() local
[all …]
/drivers/hwtracing/coresight/
Dcoresight-cti-sysfs.c830 int used = 0, reg_idx; in chan_xtrigs_in_show() local
834 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx++) { in chan_xtrigs_in_show()
835 if (chan_mask & cfg->ctiinen[reg_idx]) in chan_xtrigs_in_show()
836 used += sprintf(buf + used, "%d ", reg_idx); in chan_xtrigs_in_show()
850 int used = 0, reg_idx; in chan_xtrigs_out_show() local
854 for (reg_idx = 0; reg_idx < nr_trig_max; reg_idx++) { in chan_xtrigs_out_show()
855 if (chan_mask & cfg->ctiouten[reg_idx]) in chan_xtrigs_out_show()
856 used += sprintf(buf + used, "%d ", reg_idx); in chan_xtrigs_out_show()
/drivers/net/ethernet/intel/i40e/
Di40e_virtchnl_pf.c324 u32 reg, reg_idx; in i40e_config_irq_link_list() local
330 reg_idx = I40E_VPINT_LNKLST0(vf->vf_id); in i40e_config_irq_link_list()
332 reg_idx = I40E_VPINT_LNKLSTN( in i40e_config_irq_link_list()
338 wr32(hw, reg_idx, I40E_VPINT_LNKLST0_FIRSTQ_INDX_MASK); in i40e_config_irq_link_list()
363 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
368 reg_idx = I40E_QINT_RQCTL(pf_queue_id); in i40e_config_irq_link_list()
372 reg_idx = I40E_QINT_TQCTL(pf_queue_id); in i40e_config_irq_link_list()
397 wr32(hw, reg_idx, reg); in i40e_config_irq_link_list()
436 u32 v_idx, reg_idx, reg; in i40e_release_iwarp_qvlist() local
446 reg_idx = (msix_vf - 1) * vf->vf_id + qv_info->ceq_idx; in i40e_release_iwarp_qvlist()
[all …]
Di40e_client.c150 u32 reg_idx; in i40e_client_release_qvlist() local
155 reg_idx = I40E_PFINT_LNKLSTN(qv_info->v_idx - 1); in i40e_client_release_qvlist()
156 wr32(&pf->hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_release_qvlist()
582 u32 v_idx, i, reg_idx, reg; in i40e_client_setup_qvlist() local
602 reg_idx = I40E_PFINT_LNKLSTN(v_idx - 1); in i40e_client_setup_qvlist()
606 wr32(hw, reg_idx, I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK); in i40e_client_setup_qvlist()
612 wr32(hw, reg_idx, reg); in i40e_client_setup_qvlist()
/drivers/hwmon/
Dw83791d.c767 u8 reg_idx = 0; in store_pwmenable() local
780 reg_idx = 0; in store_pwmenable()
785 reg_idx = 0; in store_pwmenable()
790 reg_idx = 1; in store_pwmenable()
796 reg_cfg_tmp = w83791d_read(client, W83791D_REG_FAN_CFG[reg_idx]); in store_pwmenable()
800 w83791d_write(client, W83791D_REG_FAN_CFG[reg_idx], reg_cfg_tmp); in store_pwmenable()
874 u8 reg_idx = 0; in store_temp_tolerance() local
883 reg_idx = 0; in store_temp_tolerance()
888 reg_idx = 0; in store_temp_tolerance()
893 reg_idx = 1; in store_temp_tolerance()
[all …]
/drivers/perf/
Dqcom_l2_pmu.c84 #define reg_idx(reg, i) (((i) * IA_L2_REG_OFFSET) + reg##_BASE) macro
193 kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value); in cluster_pmu_counter_set_value()
203 value = kryo_l2_get_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx)); in cluster_pmu_counter_get_value()
235 kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val); in cluster_pmu_set_evcntcr()
240 kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val); in cluster_pmu_set_evtyper()
276 kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val); in cluster_pmu_set_evfilter_sys_mode()

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