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Searched refs:reg_val (Results 1 – 25 of 242) sorted by relevance

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/drivers/net/ethernet/samsung/sxgbe/
Dsxgbe_mtl.c23 u32 reg_val; in sxgbe_mtl_init() local
25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
26 reg_val &= ETS_RST; in sxgbe_mtl_init()
31 reg_val &= ETS_WRR; in sxgbe_mtl_init()
34 reg_val |= ETS_WFQ; in sxgbe_mtl_init()
37 reg_val |= ETS_DWRR; in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
44 reg_val &= RAA_SP; in sxgbe_mtl_init()
47 reg_val |= RAA_WSP; in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
[all …]
Dsxgbe_dma.c23 u32 reg_val; in sxgbe_dma_init() local
25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
33 reg_val |= SXGBE_DMA_AXI_UNDEF_BURST; in sxgbe_dma_init()
36 reg_val |= (burst_map << SXGBE_DMA_BLENMAP_LSHIFT); in sxgbe_dma_init()
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
47 u32 reg_val; in sxgbe_dma_channel_init() local
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
53 reg_val |= SXGBE_DMA_PBL_X8MODE; in sxgbe_dma_channel_init()
54 writel(reg_val, ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
56 reg_val = readl(ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cha_num)); in sxgbe_dma_channel_init()
[all …]
/drivers/input/keyboard/
Dimx_keypad.c82 unsigned short reg_val; in imx_keypad_scan_matrix() local
93 reg_val = readw(keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
94 reg_val |= 0xff00; in imx_keypad_scan_matrix()
95 writew(reg_val, keypad->mmio_base + KPDR); in imx_keypad_scan_matrix()
97 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
98 reg_val &= ~((keypad->cols_en_mask & 0xff) << 8); in imx_keypad_scan_matrix()
99 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
103 reg_val = readw(keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
104 reg_val |= (keypad->cols_en_mask & 0xff) << 8; in imx_keypad_scan_matrix()
105 writew(reg_val, keypad->mmio_base + KPCR); in imx_keypad_scan_matrix()
[all …]
/drivers/gpu/drm/amd/display/dc/
Ddc_helper.c165 uint32_t reg_val) in dmub_reg_value_burst_set_pack() argument
183 cmd_buf->write_values[offload->reg_seq_count] = reg_val; in dmub_reg_value_burst_set_pack()
248 uint32_t reg_val; in generic_reg_update_ex() local
264 reg_val = dm_read_reg(ctx, addr); in generic_reg_update_ex()
265 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_update_ex()
266 dm_write_reg(ctx, addr, reg_val); in generic_reg_update_ex()
267 return reg_val; in generic_reg_update_ex()
271 uint32_t addr, uint32_t reg_val, int n, in generic_reg_set_ex() argument
287 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in generic_reg_set_ex()
291 return dmub_reg_value_burst_set_pack(ctx, addr, reg_val); in generic_reg_set_ex()
[all …]
/drivers/media/dvb-frontends/
Daf9033_priv.h19 struct reg_val { struct
87 static const struct reg_val ofsm_init[] = {
202 static const struct reg_val tuner_init_tua9001[] = {
246 static const struct reg_val tuner_init_fc0011[] = {
309 static const struct reg_val tuner_init_fc0012[] = {
354 static const struct reg_val tuner_init_mxl5007t[] = {
391 static const struct reg_val tuner_init_tda18218[] = {
427 static const struct reg_val tuner_init_fc2580[] = {
467 static const struct reg_val ofsm_init_it9135_v1[] = {
582 static const struct reg_val tuner_init_it9135_38[] = {
[all …]
/drivers/spi/
Dspi-slave-mt27xx.c83 u32 reg_val; in mtk_spi_slave_disable_dma() local
85 reg_val = readl(mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
86 reg_val &= ~RX_DMA_EN; in mtk_spi_slave_disable_dma()
87 reg_val &= ~TX_DMA_EN; in mtk_spi_slave_disable_dma()
88 writel(reg_val, mdata->base + SPIS_DMA_CFG_REG); in mtk_spi_slave_disable_dma()
93 u32 reg_val; in mtk_spi_slave_disable_xfer() local
95 reg_val = readl(mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
96 reg_val &= ~SPIS_TX_EN; in mtk_spi_slave_disable_xfer()
97 reg_val &= ~SPIS_RX_EN; in mtk_spi_slave_disable_xfer()
98 writel(reg_val, mdata->base + SPIS_CFG_REG); in mtk_spi_slave_disable_xfer()
[all …]
Dspi-mt65xx.c183 u32 reg_val; in mtk_spi_reset() local
186 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
187 reg_val |= SPI_CMD_RST; in mtk_spi_reset()
188 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
190 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_reset()
191 reg_val &= ~SPI_CMD_RST; in mtk_spi_reset()
192 writel(reg_val, mdata->base + SPI_CMD_REG); in mtk_spi_reset()
199 u32 reg_val; in mtk_spi_prepare_message() local
207 reg_val = readl(mdata->base + SPI_CMD_REG); in mtk_spi_prepare_message()
209 reg_val |= SPI_CMD_CPHA; in mtk_spi_prepare_message()
[all …]
/drivers/net/ethernet/allwinner/
Dsun4i-emac.c95 unsigned int reg_val; in emac_update_speed() local
98 reg_val = readl(db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
99 reg_val &= ~(0x1 << 8); in emac_update_speed()
101 reg_val |= 1 << 8; in emac_update_speed()
102 writel(reg_val, db->membase + EMAC_MAC_SUPP_REG); in emac_update_speed()
108 unsigned int reg_val; in emac_update_duplex() local
111 reg_val = readl(db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
112 reg_val &= ~EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
114 reg_val |= EMAC_MAC_CTL1_DUPLEX_EN; in emac_update_duplex()
115 writel(reg_val, db->membase + EMAC_MAC_CTL1_REG); in emac_update_duplex()
[all …]
/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_vbif.c61 u32 reg_val; in dpu_hw_set_mem_type() local
79 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_mem_type()
80 reg_val &= ~(0x7 << bit_off); in dpu_hw_set_mem_type()
81 reg_val |= (value & 0x7) << bit_off; in dpu_hw_set_mem_type()
82 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_mem_type()
89 u32 reg_val; in dpu_hw_set_limit_conf() local
100 reg_val = DPU_REG_READ(c, reg_off); in dpu_hw_set_limit_conf()
101 reg_val &= ~(0xFF << bit_off); in dpu_hw_set_limit_conf()
102 reg_val |= (limit) << bit_off; in dpu_hw_set_limit_conf()
103 DPU_REG_WRITE(c, reg_off, reg_val); in dpu_hw_set_limit_conf()
[all …]
/drivers/gpu/drm/msm/hdmi/
Dhdmi_hdcp.c45 u32 reg_val; member
199 u32 reg_val, hdcp_int_status; in msm_hdmi_hdcp_irq() local
203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); in msm_hdmi_hdcp_irq()
204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; in msm_hdmi_hdcp_irq()
210 reg_val |= hdcp_int_status << 1; in msm_hdmi_hdcp_irq()
213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; in msm_hdmi_hdcp_irq()
214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); in msm_hdmi_hdcp_irq()
228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); in msm_hdmi_hdcp_irq()
230 __func__, reg_val); in msm_hdmi_hdcp_irq()
284 u32 reg_val, failure, nack0; in msm_reset_hdcp_ddc_failures() local
[all …]
/drivers/gpu/drm/i915/gem/
Di915_gem_stolen.c175 u32 reg_val = intel_uncore_read(uncore, in g4x_get_stolen_reserved() local
182 IS_GM45(i915) ? "CTG" : "ELK", reg_val); in g4x_get_stolen_reserved()
184 if ((reg_val & G4X_STOLEN_RESERVED_ENABLE) == 0) in g4x_get_stolen_reserved()
193 reg_val); in g4x_get_stolen_reserved()
195 if (!(reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK)) in g4x_get_stolen_reserved()
198 *base = (reg_val & G4X_STOLEN_RESERVED_ADDR2_MASK) << 16; in g4x_get_stolen_reserved()
200 (reg_val & G4X_STOLEN_RESERVED_ADDR1_MASK) < *base); in g4x_get_stolen_reserved()
210 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in gen6_get_stolen_reserved() local
212 drm_dbg(&i915->drm, "GEN6_STOLEN_RESERVED = %08x\n", reg_val); in gen6_get_stolen_reserved()
214 if (!(reg_val & GEN6_STOLEN_RESERVED_ENABLE)) in gen6_get_stolen_reserved()
[all …]
/drivers/net/ethernet/cavium/liquidio/
Dcn23xx_vf_device.c68 u64 reg_val = octeon_read_csr64(oct, in cn23xx_vf_reset_io_queues() local
70 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_vf_reset_io_queues()
71 !(READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_QUIET) && in cn23xx_vf_reset_io_queues()
73 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
83 WRITE_ONCE(reg_val, READ_ONCE(reg_val) & in cn23xx_vf_reset_io_queues()
86 READ_ONCE(reg_val)); in cn23xx_vf_reset_io_queues()
88 WRITE_ONCE(reg_val, octeon_read_csr64( in cn23xx_vf_reset_io_queues()
90 if (READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) { in cn23xx_vf_reset_io_queues()
153 u32 reg_val; in cn23xx_vf_setup_global_output_regs() local
160 reg_val = in cn23xx_vf_setup_global_output_regs()
[all …]
Dcn23xx_pf_device.c305 u64 reg_val; in cn23xx_setup_global_mac_regs() local
314 reg_val = in cn23xx_setup_global_mac_regs()
319 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF_PASS_1_1; in cn23xx_setup_global_mac_regs()
322 reg_val = pf_num * CN23XX_MAX_RINGS_PER_PF; in cn23xx_setup_global_mac_regs()
326 reg_val = reg_val | in cn23xx_setup_global_mac_regs()
330 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_RPVF_BIT_POS); in cn23xx_setup_global_mac_regs()
334 reg_val |= (temp << CN23XX_PKT_MAC_CTL_RINFO_NVFS_BIT_POS); in cn23xx_setup_global_mac_regs()
338 reg_val); in cn23xx_setup_global_mac_regs()
368 u64 reg_val = octeon_read_csr64(oct, in cn23xx_reset_io_queues() local
370 while ((READ_ONCE(reg_val) & CN23XX_PKT_INPUT_CTL_RST) && in cn23xx_reset_io_queues()
[all …]
/drivers/ata/
Dahci_sunxi.c55 u32 reg_val; in sunxi_clrbits() local
57 reg_val = readl(reg); in sunxi_clrbits()
58 reg_val &= ~(clr_val); in sunxi_clrbits()
59 writel(reg_val, reg); in sunxi_clrbits()
64 u32 reg_val; in sunxi_setbits() local
66 reg_val = readl(reg); in sunxi_setbits()
67 reg_val |= set_val; in sunxi_setbits()
68 writel(reg_val, reg); in sunxi_setbits()
73 u32 reg_val; in sunxi_clrsetbits() local
75 reg_val = readl(reg); in sunxi_clrsetbits()
[all …]
/drivers/video/backlight/
Dlm3639_bl.c50 unsigned int reg_val; in lm3639_chip_init() local
60 reg_val = (pdata->pin_pwm & 0x40) | pdata->pin_strobe | pdata->pin_tx; in lm3639_chip_init()
61 ret = regmap_update_bits(pchip->regmap, REG_IO_CTRL, 0x7C, reg_val); in lm3639_chip_init()
76 reg_val = pdata->fled_pins; in lm3639_chip_init()
77 reg_val |= pdata->bled_pins; in lm3639_chip_init()
79 reg_val = pdata->fled_pins; in lm3639_chip_init()
80 reg_val |= pdata->bled_pins | 0x01; in lm3639_chip_init()
83 ret = regmap_update_bits(pchip->regmap, REG_ENABLE, 0x79, reg_val); in lm3639_chip_init()
97 unsigned int reg_val; in lm3639_bled_update_status() local
101 ret = regmap_read(pchip->regmap, REG_FLAG, &reg_val); in lm3639_bled_update_status()
[all …]
Dadp8860_bl.c141 uint8_t reg_val; in adp8860_set_bits() local
146 ret = adp8860_read(client, reg, &reg_val); in adp8860_set_bits()
148 if (!ret && ((reg_val & bit_mask) != bit_mask)) { in adp8860_set_bits()
149 reg_val |= bit_mask; in adp8860_set_bits()
150 ret = adp8860_write(client, reg, reg_val); in adp8860_set_bits()
160 uint8_t reg_val; in adp8860_clr_bits() local
165 ret = adp8860_read(client, reg, &reg_val); in adp8860_clr_bits()
167 if (!ret && (reg_val & bit_mask)) { in adp8860_clr_bits()
168 reg_val &= ~bit_mask; in adp8860_clr_bits()
169 ret = adp8860_write(client, reg, reg_val); in adp8860_clr_bits()
[all …]
/drivers/edac/
Ddmc520_edac.c255 u32 reg_val = readl(reg_base + REG_OFFSET_FEATURE_CONFIG); in dmc520_is_ecc_enabled() local
257 return FIELD_GET(REG_FIELD_DRAM_ECC_ENABLED, reg_val); in dmc520_is_ecc_enabled()
263 u32 reg_val, scrub_cfg; in dmc520_get_scrub_type() local
265 reg_val = dmc520_read_reg(pvt, REG_OFFSET_SCRUB_CONTROL0_NOW); in dmc520_get_scrub_type()
266 scrub_cfg = FIELD_GET(SCRUB_TRIGGER0_NEXT_MASK, reg_val); in dmc520_get_scrub_type()
280 u32 reg_val; in dmc520_get_memory_width() local
282 reg_val = dmc520_read_reg(pvt, REG_OFFSET_FORMAT_CONTROL); in dmc520_get_memory_width()
283 mem_width_field = FIELD_GET(MEMORY_WIDTH_MASK, reg_val); in dmc520_get_memory_width()
296 u32 reg_val; in dmc520_get_mtype() local
298 reg_val = dmc520_read_reg(pvt, REG_OFFSET_MEMORY_TYPE_NOW); in dmc520_get_mtype()
[all …]
/drivers/mtd/nand/raw/
Domap_elm.c103 u32 reg_val; in elm_config() local
121 reg_val = (bch_type & ECC_BCH_LEVEL_MASK) | (ELM_ECC_SIZE << 16); in elm_config()
122 elm_write_reg(info, ELM_LOCATION_CONFIG, reg_val); in elm_config()
142 u32 reg_val; in elm_configure_page_mode() local
144 reg_val = elm_read_reg(info, ELM_PAGE_CTRL); in elm_configure_page_mode()
146 reg_val |= BIT(index); /* enable page mode */ in elm_configure_page_mode()
148 reg_val &= ~BIT(index); /* disable page mode */ in elm_configure_page_mode()
150 elm_write_reg(info, ELM_PAGE_CTRL, reg_val); in elm_configure_page_mode()
251 u32 reg_val; in elm_start_processing() local
261 reg_val = elm_read_reg(info, offset); in elm_start_processing()
[all …]
/drivers/media/i2c/
Dlm3646.c102 unsigned int reg_val; in lm3646_get_ctrl() local
108 rval = regmap_read(flash->regmap, REG_FLAG, &reg_val); in lm3646_get_ctrl()
113 if (reg_val & FAULT_TIMEOUT) in lm3646_get_ctrl()
115 if (reg_val & FAULT_SHORT_CIRCUIT) in lm3646_get_ctrl()
117 if (reg_val & FAULT_UVLO) in lm3646_get_ctrl()
119 if (reg_val & FAULT_IVFM) in lm3646_get_ctrl()
121 if (reg_val & FAULT_OCP) in lm3646_get_ctrl()
123 if (reg_val & FAULT_OVERTEMP) in lm3646_get_ctrl()
125 if (reg_val & FAULT_NTC_TRIP) in lm3646_get_ctrl()
127 if (reg_val & FAULT_OVP) in lm3646_get_ctrl()
[all …]
/drivers/net/wireless/ath/ath10k/
Dhw.c743 u32 addr, reg_val, mem_val; in ath10k_hw_qca6174_enable_pll_clock() local
760 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
765 if (MS(reg_val, EFUSE_XTAL_SEL) > ATH10K_HW_REFCLK_COUNT) in ath10k_hw_qca6174_enable_pll_clock()
768 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; in ath10k_hw_qca6174_enable_pll_clock()
772 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
776 reg_val &= ~(BB_PLL_CONFIG_FRAC_MASK | BB_PLL_CONFIG_OUTDIV_MASK); in ath10k_hw_qca6174_enable_pll_clock()
777 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | in ath10k_hw_qca6174_enable_pll_clock()
779 ret = ath10k_bmi_write_soc_reg(ar, addr, reg_val); in ath10k_hw_qca6174_enable_pll_clock()
785 ret = ath10k_bmi_read_soc_reg(ar, addr, &reg_val); in ath10k_hw_qca6174_enable_pll_clock()
789 reg_val &= ~WLAN_PLL_SETTLE_TIME_MASK; in ath10k_hw_qca6174_enable_pll_clock()
[all …]
/drivers/gpu/drm/amd/display/dmub/src/
Ddmub_reg.c76 uint32_t reg_val; in dmub_reg_update() local
84 reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_update()
85 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in dmub_reg_update()
86 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_update()
89 void dmub_reg_set(struct dmub_srv *srv, uint32_t addr, uint32_t reg_val, int n, in dmub_reg_set() argument
100 reg_val = (reg_val & ~field_value_mask.mask) | field_value_mask.value; in dmub_reg_set()
101 srv->funcs.reg_write(srv->user_ctx, addr, reg_val); in dmub_reg_set()
107 uint32_t reg_val = srv->funcs.reg_read(srv->user_ctx, addr); in dmub_reg_get() local
108 *field_value = get_reg_field_value_ex(reg_val, mask, shift); in dmub_reg_get()
/drivers/power/supply/
Dcw2015_battery.c99 unsigned int reg_val; in cw_update_profile() local
103 ret = regmap_read(cw_bat->regmap, CW2015_REG_MODE, &reg_val); in cw_update_profile()
107 reset_val = reg_val; in cw_update_profile()
108 if ((reg_val & CW2015_MODE_SLEEP_MASK) == CW2015_MODE_SLEEP) { in cw_update_profile()
122 reg_val |= CW2015_CONFIG_UPDATE_FLG; in cw_update_profile()
123 reg_val &= ~CW2015_MASK_ATHD; in cw_update_profile()
124 reg_val |= CW2015_ATHD(cw_bat->alert_level); in cw_update_profile()
125 ret = regmap_write(cw_bat->regmap, CW2015_REG_CONFIG, reg_val); in cw_update_profile()
131 reg_val = reset_val | CW2015_MODE_RESTART; in cw_update_profile()
132 ret = regmap_write(cw_bat->regmap, CW2015_REG_MODE, reg_val); in cw_update_profile()
[all …]
/drivers/clk/bcm/
Dclk-kona.c42 static inline u32 bitfield_extract(u32 reg_val, u32 shift, u32 width) in bitfield_extract() argument
44 return (reg_val & bitfield_mask(shift, width)) >> shift; in bitfield_extract()
48 static inline u32 bitfield_replace(u32 reg_val, u32 shift, u32 width, u32 val) in bitfield_replace() argument
52 return (reg_val & ~mask) | (val << shift); in bitfield_replace()
137 __ccu_write(struct ccu_data *ccu, u32 reg_offset, u32 reg_val) in __ccu_write() argument
139 writel(reg_val, ccu->base + reg_offset); in __ccu_write()
337 u32 reg_val; in policy_init() local
339 reg_val = __ccu_read(ccu, offset); in policy_init()
340 reg_val |= mask; in policy_init()
341 __ccu_write(ccu, offset, reg_val); in policy_init()
[all …]
/drivers/mfd/
Dadp5520.c75 uint8_t reg_val; in __adp5520_ack_bits() local
80 ret = __adp5520_read(client, reg, &reg_val); in __adp5520_ack_bits()
83 reg_val |= bit_mask; in __adp5520_ack_bits()
84 ret = __adp5520_write(client, reg, reg_val); in __adp5520_ack_bits()
106 uint8_t reg_val; in adp5520_set_bits() local
111 ret = __adp5520_read(chip->client, reg, &reg_val); in adp5520_set_bits()
113 if (!ret && ((reg_val & bit_mask) != bit_mask)) { in adp5520_set_bits()
114 reg_val |= bit_mask; in adp5520_set_bits()
115 ret = __adp5520_write(chip->client, reg, reg_val); in adp5520_set_bits()
126 uint8_t reg_val; in adp5520_clr_bits() local
[all …]
/drivers/staging/hikey9xx/
Dhi6421v600-regulator.c60 u32 reg_val; in hi6421_spmi_regulator_is_enabled() local
62 reg_val = hi6421_spmi_pmic_read(pmic, rdev->desc->enable_reg); in hi6421_spmi_regulator_is_enabled()
67 reg_val, (reg_val & rdev->desc->enable_mask)); in hi6421_spmi_regulator_is_enabled()
69 return ((reg_val & rdev->desc->enable_mask) != 0); in hi6421_spmi_regulator_is_enabled()
116 u32 reg_val, selector; in hi6421_spmi_regulator_get_voltage_sel() local
119 reg_val = hi6421_spmi_pmic_read(pmic, rdev->desc->vsel_reg); in hi6421_spmi_regulator_get_voltage_sel()
121 selector = (reg_val & rdev->desc->vsel_mask) >> (ffs(rdev->desc->vsel_mask) - 1); in hi6421_spmi_regulator_get_voltage_sel()
125 rdev->desc->vsel_reg, reg_val, selector, in hi6421_spmi_regulator_get_voltage_sel()
136 u32 reg_val; in hi6421_spmi_regulator_set_voltage_sel() local
141 reg_val = selector << (ffs(rdev->desc->vsel_mask) - 1); in hi6421_spmi_regulator_set_voltage_sel()
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