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Searched refs:reg_write (Results 1 – 25 of 137) sorted by relevance

123456

/drivers/firewire/
Dinit_ohci1394_dma.c40 static inline void reg_write(const struct ohci *ohci, int offset, u32 data) in reg_write() function
58 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | 0x00008000); in get_phy_reg()
75 reg_write(ohci, OHCI1394_PhyControl, (addr << 8) | data | 0x00004000); in set_phy_reg()
89 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset); in init_ohci1394_soft_reset()
114 reg_write(ohci, OHCI1394_BusOptions, bus_options); in init_ohci1394_initialize()
117 reg_write(ohci, OHCI1394_NodeID, 0x0000ffc0); in init_ohci1394_initialize()
120 reg_write(ohci, OHCI1394_HCControlSet, in init_ohci1394_initialize()
124 reg_write(ohci, OHCI1394_LinkControlClear, 0xffffffff); in init_ohci1394_initialize()
127 reg_write(ohci, OHCI1394_LinkControlSet, in init_ohci1394_initialize()
131 reg_write(ohci, OHCI1394_LinkControlClear, 0x00000400); in init_ohci1394_initialize()
[all …]
Dohci.c572 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data) in reg_write() function
599 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr)); in read_phy_reg()
625 reg_write(ohci, OHCI1394_PhyControl, in write_phy_reg()
717 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE); in ar_context_link_page()
739 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN); in ar_context_abort()
1076 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1); in ar_context_run()
1077 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN); in ar_context_run()
1255 reg_write(ohci, COMMAND_PTR(ctx->regs), in context_run()
1257 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0); in context_run()
1258 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra); in context_run()
[all …]
Dnosy.c214 reg_write(struct pcilynx *lynx, int offset, u32 data) in reg_write() function
228 reg_write(lynx, offset, (reg_read(lynx, offset) | mask)); in reg_set_bits()
239 reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20, pcl_bus); in run_pcl()
240 reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20, in run_pcl()
257 reg_write(lynx, LINK_PHY, LINK_PHY_WRITE | in set_phy_reg()
475 reg_write(lynx, LINK_INT_STATUS, link_int_status); in irq_handler()
485 reg_write(lynx, PCI_INT_STATUS, pci_int_status); in irq_handler()
506 reg_write(lynx, PCI_INT_ENABLE, 0); in remove_card()
599 reg_write(lynx, DMA0_CHAN_CTRL, 0); in add_card()
600 reg_write(lynx, DMA_GLOBAL_REGISTER, 0x00 << 24); in add_card()
[all …]
/drivers/media/i2c/
Drj54n1cb0c.c446 static int reg_write(struct i2c_client *client, const u16 reg, in reg_write() function
472 return reg_write(client, reg, (ret & ~mask) | (data & mask)); in reg_set()
481 ret = reg_write(client, rv->reg, rv->val); in reg_write_multiple()
515 ret = reg_write(client, reg_xy, in rj54n1_set_rect()
520 ret = reg_write(client, reg_x, width & 0xff); in rj54n1_set_rect()
522 ret = reg_write(client, reg_y, height & 0xff); in rj54n1_set_rect()
533 int ret = reg_write(client, RJ54N1_INIT_START, 1); in rj54n1_commit()
536 ret = reg_write(client, RJ54N1_INIT_START, 0); in rj54n1_commit()
725 ret = reg_write(client, RJ54N1_RESIZE_HOLD_L, resize & 0xff); in rj54n1_sensor_scale()
727 ret = reg_write(client, RJ54N1_RESIZE_HOLD_H, resize >> 8); in rj54n1_sensor_scale()
[all …]
Dak881x.c40 static int reg_write(struct i2c_client *client, const u8 reg, in reg_write() function
52 return reg_write(client, reg, (ret & ~mask) | (data & mask)); in reg_set()
86 if (reg_write(client, reg->reg, reg->val) < 0) in ak881x_s_register()
191 reg_write(client, AK881X_DAC_MODE, dac); in ak881x_s_stream()
196 reg_write(client, AK881X_DAC_MODE, 0); in ak881x_s_stream()
288 reg_write(client, AK881X_INTERFACE_MODE, ifmode | (20 << 3)); in ak881x_probe()
Dmt9m001.c120 static int reg_write(struct i2c_client *client, const u8 reg, in reg_write() function
134 return reg_write(client, reg, ret | data); in reg_set()
145 return reg_write(client, reg, ret & ~data); in reg_clear()
159 int ret = reg_write(client, regs[i].reg, regs[i].data); in multi_reg_write()
233 ret = reg_write(client, MT9M001_OUTPUT_CONTROL, 2); in mt9m001_s_stream()
238 reg_write(client, MT9M001_OUTPUT_CONTROL, 0); in mt9m001_s_stream()
443 if (reg_write(client, reg->reg, reg->val) < 0) in mt9m001_s_register()
532 ret = reg_write(client, MT9M001_GLOBAL_GAIN, data); in mt9m001_s_ctrl()
549 ret = reg_write(client, MT9M001_GLOBAL_GAIN, data); in mt9m001_s_ctrl()
562 ret = reg_write(client, MT9M001_SHUTTER_WIDTH, shutter); in mt9m001_s_ctrl()
[all …]
/drivers/media/tuners/
Dqm1d1c0042.c64 static int reg_write(struct qm1d1c0042_state *state, u8 reg, u8 val) in reg_write() function
107 return reg_write(state, 0x03, state->regs[0x03]); in qm1d1c0042_set_srch_mode()
117 ret = reg_write(state, 0x01, state->regs[0x01]); in qm1d1c0042_wakeup()
119 ret = reg_write(state, 0x05, state->regs[0x05]); in qm1d1c0042_wakeup()
205 ret = reg_write(state, 0x02, val); in qm1d1c0042_set_params()
213 ret = reg_write(state, 0x06, state->regs[0x06]); in qm1d1c0042_set_params()
219 ret = reg_write(state, 0x07, state->regs[0x07]); in qm1d1c0042_set_params()
230 ret = reg_write(state, 0x08, val); in qm1d1c0042_set_params()
251 ret = reg_write(state, 0x09, state->regs[0x09]); in qm1d1c0042_set_params()
253 ret = reg_write(state, 0x0a, state->regs[0x0a]); in qm1d1c0042_set_params()
[all …]
Dmxl301rf.c45 static int reg_write(struct mxl301rf_state *state, u8 reg, u8 val) in reg_write() function
83 ret = reg_write(state, 0x14, 0x01); in mxl301rf_get_rf_strength()
215 ret = reg_write(state, 0x1a, 0x0d); in mxl301rf_set_params()
259 ret = reg_write(state, 0x01, 0x01); in mxl301rf_init()
/drivers/media/usb/gspca/
Dspca505.c533 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
577 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
619 reg_write(gspca_dev, 0x05, 0x00, (255 - brightness) >> 6); in setbrightness()
620 reg_write(gspca_dev, 0x05, 0x01, (255 - brightness) << 2); in setbrightness()
651 ret = reg_write(gspca_dev, 0x06, 0x16, 0x0a); in sd_start()
654 reg_write(gspca_dev, 0x05, 0xc2, 0x12); in sd_start()
659 reg_write(gspca_dev, 0x02, 0x00, 0x00); in sd_start()
662 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x00, mode_tb[mode][0]); in sd_start()
663 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x06, mode_tb[mode][1]); in sd_start()
664 reg_write(gspca_dev, SPCA50X_REG_COMPRESS, 0x07, mode_tb[mode][2]); in sd_start()
[all …]
Dspca508.c1231 static int reg_write(struct gspca_dev *gspca_dev, u16 index, u16 value) in reg_write() function
1278 ret = reg_write(gspca_dev, 0x8802, reg >> 8); in ssi_w()
1281 ret = reg_write(gspca_dev, 0x8801, reg & 0x00ff); in ssi_w()
1285 ret = reg_write(gspca_dev, 0x8805, val & 0x00ff); in ssi_w()
1290 ret = reg_write(gspca_dev, 0x8800, val); in ssi_w()
1325 ret = reg_write(gspca_dev, (*data)[1], in write_vector()
1393 reg_write(gspca_dev, 0x8500, mode); in sd_start()
1397 reg_write(gspca_dev, 0x8700, 0x28); /* clock */ in sd_start()
1402 reg_write(gspca_dev, 0x8700, 0x23); /* clock */ in sd_start()
1405 reg_write(gspca_dev, 0x8112, 0x10 | 0x20); in sd_start()
[all …]
Dspca501.c1745 static int reg_write(struct gspca_dev *gspca_dev, in reg_write() function
1769 ret = reg_write(gspca_dev, data[i][0], data[i][2], in write_vector()
1783 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x12, val); in setbrightness()
1788 reg_write(gspca_dev, 0x00, 0x00, (val >> 8) & 0xff); in setcontrast()
1789 reg_write(gspca_dev, 0x00, 0x01, val & 0xff); in setcontrast()
1794 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x0c, val); in setcolors()
1799 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x11, val); in setblue_balance()
1804 reg_write(gspca_dev, SPCA501_REG_CCDSP, 0x13, val); in setred_balance()
1880 reg_write(gspca_dev, SPCA50X_REG_USB, 0x6, 0x94); in sd_start()
1883 reg_write(gspca_dev, SPCA50X_REG_USB, 0x07, 0x004a); in sd_start()
[all …]
/drivers/gpu/drm/i2c/
Dtda998x_drv.c650 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) in reg_write() function
694 reg_write(priv, reg, old_val | val); in reg_set()
704 reg_write(priv, reg, old_val & ~val); in reg_clear()
711 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); in tda998x_reset()
713 reg_write(priv, REG_SOFTRESET, 0); in tda998x_reset()
721 reg_write(priv, REG_PLL_SERIAL_1, 0x00); in tda998x_reset()
722 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); in tda998x_reset()
723 reg_write(priv, REG_PLL_SERIAL_3, 0x00); in tda998x_reset()
724 reg_write(priv, REG_SERIALIZER, 0x00); in tda998x_reset()
725 reg_write(priv, REG_BUFFER_OUT, 0x00); in tda998x_reset()
[all …]
/drivers/net/dsa/
Dmv88e6060.c22 static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val) in reg_write() function
63 ret = reg_write(priv, REG_PORT(i), PORT_CONTROL, in mv88e6060_switch_reset()
73 ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, in mv88e6060_switch_reset()
105 ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL, in mv88e6060_setup_global()
112 return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL, in mv88e6060_setup_global()
129 ret = reg_write(priv, addr, PORT_CONTROL, in mv88e6060_setup_port()
143 ret = reg_write(priv, addr, PORT_VLAN_MAP, in mv88e6060_setup_port()
156 return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p)); in mv88e6060_setup_port()
174 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val); in mv88e6060_setup_addr()
178 ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23, in mv88e6060_setup_addr()
[all …]
/drivers/media/pci/tw686x/
Dtw686x-core.c108 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en); in tw686x_disable_channel()
109 reg_write(dev, DMA_CMD, dma_cmd); in tw686x_disable_channel()
133 reg_write(dev, DMA_CHANNEL_ENABLE, dev->pending_dma_en); in tw686x_dma_delay()
134 reg_write(dev, DMA_CMD, dev->pending_dma_cmd); in tw686x_dma_delay()
156 reg_write(dev, DMA_CHANNEL_ENABLE, dma_en & ~ch_mask); in tw686x_reset_channels()
162 reg_write(dev, DMA_CMD, dma_cmd & ~ch_mask); in tw686x_reset_channels()
300 reg_write(dev, SYS_SOFT_RST, 0x0f); in tw686x_probe()
303 reg_write(dev, SRST[0], 0x3f); in tw686x_probe()
305 reg_write(dev, SRST[1], 0x3f); in tw686x_probe()
308 reg_write(dev, DMA_CMD, 0); in tw686x_probe()
[all …]
Dtw686x-video.c123 reg_write(dev, reg, vc->dma_descs[pb].phys); in tw686x_memcpy_dma_alloc()
168 reg_write(vc->dev, reg, phys); in tw686x_contig_buf_refill()
289 reg_write(dev, reg, desc->phys); in tw686x_sg_dma_alloc()
408 reg_write(vc->dev, VIDEO_FIELD_CTRL[vc->ch], fps_map[i]); in tw686x_set_framerate()
599 reg_write(dev, BRIGHT[ch], ctrl->val & 0xff); in tw686x_s_ctrl()
603 reg_write(dev, CONTRAST[ch], ctrl->val); in tw686x_s_ctrl()
607 reg_write(dev, SAT_U[ch], ctrl->val); in tw686x_s_ctrl()
608 reg_write(dev, SAT_V[ch], ctrl->val); in tw686x_s_ctrl()
612 reg_write(dev, HUE[ch], ctrl->val & 0xff); in tw686x_s_ctrl()
725 reg_write(vc->dev, VDMA_CHANNEL_CONFIG[vc->ch], val); in tw686x_set_format()
[all …]
Dtw686x-audio.c74 reg_write(dev, reg, next->dma); in tw686x_audio_irq()
159 reg_write(dev, AUDIO_CONTROL2, reg); in tw686x_pcm_prepare()
170 reg_write(dev, AUDIO_CONTROL1, reg); in tw686x_pcm_prepare()
198 reg_write(dev, ADMA_P_ADDR[ac->ch], p_buf->dma); in tw686x_pcm_prepare()
199 reg_write(dev, ADMA_B_ADDR[ac->ch], b_buf->dma); in tw686x_pcm_prepare()
337 reg_write(dev, reg, ac->dma_descs[pb].phys); in tw686x_audio_dma_alloc()
351 reg_write(dev, DMA_CMD, dma_cmd & ~0xff00); in tw686x_audio_free()
352 reg_write(dev, DMA_CHANNEL_ENABLE, dma_ch_mask & ~0xff00); in tw686x_audio_free()
368 reg_write(dev, AUDIO_CONTROL1, BIT(0)); in tw686x_audio_init()
/drivers/base/regmap/
Dregmap-mmio.c23 void (*reg_write)(struct regmap_mmio_context *ctx, member
126 ctx->reg_write(ctx, reg, val); in regmap_mmio_write()
205 .reg_write = regmap_mmio_write,
251 ctx->reg_write = regmap_mmio_write8; in regmap_mmio_gen_context()
255 ctx->reg_write = regmap_mmio_write16le; in regmap_mmio_gen_context()
259 ctx->reg_write = regmap_mmio_write32le; in regmap_mmio_gen_context()
264 ctx->reg_write = regmap_mmio_write64le; in regmap_mmio_gen_context()
279 ctx->reg_write = regmap_mmio_write8; in regmap_mmio_gen_context()
283 ctx->reg_write = regmap_mmio_write16be; in regmap_mmio_gen_context()
287 ctx->reg_write = regmap_mmio_write32be; in regmap_mmio_gen_context()
/drivers/media/pci/sta2x11/
Dsta2x11_vip.c203 static inline void reg_write(struct sta2x11_vip *vip, unsigned int reg, u32 val) in reg_write() function
222 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) | DVP_CTL_ENA); in start_dma()
224 reg_write(vip, DVP_VTP, (u32)vip_buf->dma); in start_dma()
225 reg_write(vip, DVP_VBP, (u32)vip_buf->dma + offset); in start_dma()
337 reg_write(vip, DVP_ITM, DVP_IT_VSB | DVP_IT_VST); in start_streaming()
353 reg_write(vip, DVP_CTL, reg_read(vip, DVP_CTL) & ~DVP_CTL_ENA); in stop_streaming()
355 reg_write(vip, DVP_ITM, 0); in stop_streaming()
684 reg_write(vip, DVP_TFO, 0); in vidioc_s_fmt_vid_cap()
686 reg_write(vip, DVP_BFO, 0); in vidioc_s_fmt_vid_cap()
688 reg_write(vip, DVP_TFS, t_stop); in vidioc_s_fmt_vid_cap()
[all …]
/drivers/iio/dac/
Dad5592r-base.c56 st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); in ad5592r_gpio_set()
71 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); in ad5592r_gpio_direction_input()
75 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); in ad5592r_gpio_direction_input()
99 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_SET, st->gpio_val); in ad5592r_gpio_direction_output()
103 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_OUT_EN, st->gpio_out); in ad5592r_gpio_direction_output()
107 ret = st->ops->reg_write(st, AD5592R_REG_GPIO_IN_EN, st->gpio_in); in ad5592r_gpio_direction_output()
170 st->ops->reg_write(st, AD5592R_REG_RESET, 0xdac); in ad5592r_reset()
249 ret = ops->reg_write(st, AD5592R_REG_PULLDOWN, pulldown); in ad5592r_set_channel_modes()
253 ret = ops->reg_write(st, AD5592R_REG_TRISTATE, tristate); in ad5592r_set_channel_modes()
258 ret = ops->reg_write(st, AD5592R_REG_DAC_EN, dac); in ad5592r_set_channel_modes()
[all …]
/drivers/watchdog/
Dstm32_iwdg.c82 static inline void reg_write(void __iomem *base, u32 reg, u32 val) in reg_write() function
106 reg_write(wdt->regs, IWDG_KR, KR_KEY_EWA); in stm32_iwdg_start()
109 reg_write(wdt->regs, IWDG_PR, iwdg_pr); in stm32_iwdg_start()
110 reg_write(wdt->regs, IWDG_RLR, iwdg_rlr); in stm32_iwdg_start()
111 reg_write(wdt->regs, IWDG_KR, KR_KEY_ENABLE); in stm32_iwdg_start()
123 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); in stm32_iwdg_start()
135 reg_write(wdt->regs, IWDG_KR, KR_KEY_RELOAD); in stm32_iwdg_ping()
/drivers/soundwire/
Dqcom.c110 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val); member
197 ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_WR_CMD, val); in qcom_swrm_cmd_fifo_wr_cmd()
230 ret = ctrl->reg_write(ctrl, SWRM_CMD_FIFO_RD_CMD, val); in qcom_swrm_cmd_fifo_rd_cmd()
286 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1); in qcom_swrm_irq_handler()
298 ctrl->reg_write(ctrl, SWRM_INTERRUPT_CLEAR, sts); in qcom_swrm_irq_handler()
317 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val); in qcom_swrm_init()
320 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 0); in qcom_swrm_init()
323 ctrl->reg_write(ctrl, SWRM_INTERRUPT_MASK_ADDR, in qcom_swrm_init()
329 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val); in qcom_swrm_init()
332 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR, SWRM_RD_WR_CMD_RETRIES); in qcom_swrm_init()
[all …]
/drivers/i2c/busses/
Di2c-pasemi.c52 static inline void reg_write(struct pasemi_smbus *smbus, int reg, int val) in reg_write() function
68 #define TXFIFO_WR(smbus, reg) reg_write((smbus), REG_MTXFIFO, (reg))
76 reg_write(smbus, REG_SMSTA, status); in pasemi_smb_clear()
97 reg_write(smbus, REG_SMSTA, status); in pasemi_smb_waitready()
102 reg_write(smbus, REG_SMSTA, SMSTA_XEN); in pasemi_smb_waitready()
151 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | in pasemi_i2c_xfer_msg()
318 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | in pasemi_smb_xfer()
370 reg_write(smbus, REG_CTL, (CTL_MTR | CTL_MRR | in pasemi_smb_probe()
/drivers/thunderbolt/
Dnvm.c122 nvmem_reg_write_t reg_write) in tb_nvm_add_non_active() argument
130 config.reg_write = reg_write; in tb_nvm_add_non_active()
/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dbtcoex.c108 } reg_write; in brcmf_btcoex_params_write() local
110 reg_write.addr = cpu_to_le32(addr); in brcmf_btcoex_params_write()
111 reg_write.data = cpu_to_le32(data); in brcmf_btcoex_params_write()
113 &reg_write, sizeof(reg_write)); in brcmf_btcoex_params_write()
/drivers/media/dvb-frontends/
Dtc90522.c46 reg_write(struct tc90522_state *state, const struct reg_val *regs, int num) in reg_write() function
107 return reg_write(fe->demodulator_priv, set_tsid, ARRAY_SIZE(set_tsid)); in tc90522s_set_tsid()
119 return reg_write(fe->demodulator_priv, &rv, 1); in tc90522t_set_layers()
495 ret = reg_write(state, &reset_sat, 1); in tc90522_set_frontend()
500 ret = reg_write(state, &reset_ter, 1); in tc90522_set_frontend()
559 return reg_write(state, rv, num); in tc90522_set_if_agc()
572 ret = reg_write(state, &sleep_sat, 1); in tc90522_sleep()
574 ret = reg_write(state, &sleep_ter, 1); in tc90522_sleep()
605 ret = reg_write(state, &wakeup_sat, 1); in tc90522_init()
607 ret = reg_write(state, &wakeup_ter, 1); in tc90522_init()

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