| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_resource.c | 375 static const struct resource_caps res_cap = { variable
831 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_resource_destruct()
961 pool->base.res_cap = &res_cap; in dce80_construct()
969 pool->base.pipe_count = res_cap.num_timing_generator; in dce80_construct()
970 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce80_construct()
1086 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce80_construct()
1160 pool->base.res_cap = &res_cap_81; in dce81_construct()
1284 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce81_construct()
1358 pool->base.res_cap = &res_cap_83; in dce83_construct()
1478 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce83_construct()
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| /drivers/gpu/drm/amd/display/dc/dce60/ |
| D | dce60_resource.c | 370 static const struct resource_caps res_cap = { variable
826 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_resource_destruct()
956 pool->base.res_cap = &res_cap; in dce60_construct()
964 pool->base.pipe_count = res_cap.num_timing_generator; in dce60_construct()
965 pool->base.timing_generator_count = res_cap.num_timing_generator; in dce60_construct()
1077 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce60_construct()
1151 pool->base.res_cap = &res_cap_61; in dce61_construct()
1275 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce61_construct()
1349 pool->base.res_cap = &res_cap_64; in dce64_construct()
1469 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce64_construct()
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| /drivers/gpu/drm/amd/display/dc/dce100/ |
| D | dce100_resource.c | 374 static const struct resource_caps res_cap = { variable
783 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_destruct()
995 pool->base.res_cap = &res_cap; in dce100_resource_construct()
1070 pool->base.pipe_count = res_cap.num_timing_generator; in dce100_resource_construct()
1071 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce100_resource_construct()
1124 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce100_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_resource.c | 1220 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn30_resource_destruct()
1250 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn30_resource_destruct()
1263 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn30_resource_destruct()
1268 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn30_resource_destruct()
1275 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn30_resource_destruct()
1298 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) { in dcn30_resource_destruct()
1348 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_dwbc_create()
1373 uint32_t pipe_count = pool->res_cap->num_dwb; in dcn30_mmhubbub_create()
1655 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_acquire_post_bldn_3dlut()
1685 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) { in dcn30_release_post_bldn_3dlut()
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| D | dcn30_hwseq.c | 386 ASSERT(stream->num_wb_info <= dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
416 ASSERT(wb_info.dwb_pipe_inst < dc->res_pool->res_cap->num_dwb); in dcn30_program_all_writeback_pipes_in_tree()
516 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn30_init_hw()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_resource.c | 506 static const struct resource_caps res_cap = { variable
633 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_destruct()
1074 pool->base.res_cap = &res_cap; in dce120_resource_construct()
1078 pool->base.pipe_count = res_cap.num_timing_generator; in dce120_resource_construct()
1079 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce120_resource_construct()
1222 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce120_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 921 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn21_resource_destruct()
951 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_destruct()
964 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn21_resource_destruct()
969 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn21_resource_destruct()
976 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn21_resource_destruct()
1413 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator; in update_bw_bounding_box()
1807 pool->base.res_cap = &res_cap_rn; in dcn21_resource_construct()
1811 pool->base.res_cap = &res_cap_rn_FPGA_4pipe; in dcn21_resource_construct()
1822 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn21_resource_construct()
2033 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn21_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_resource.c | 549 static const struct resource_caps res_cap = { variable
1011 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_destruct()
1355 pool->base.res_cap = &rv2_res_cap; in dcn10_resource_construct()
1357 pool->base.res_cap = &res_cap; in dcn10_resource_construct()
1371 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dcn10_resource_construct()
1604 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn10_resource_construct()
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| D | dcn10_hw_sequencer.c | 396 for (i = 0; i < pool->res_cap->num_dsc; i++) { in dcn10_log_hw_state()
1194 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn10_init_pipes()
1349 for (i = 0; i < res_pool->res_cap->num_dsc; i++) in dcn10_init_hw()
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| /drivers/gpu/drm/amd/display/dc/dce112/ |
| D | dce112_resource.c | 804 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_destruct()
1232 pool->base.res_cap = dce112_resource_cap(&ctx->asic_id); in dce112_resource_construct()
1239 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1240 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce112_resource_construct()
1371 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce112_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_resource.c | 1470 for (i = 0; i < pool->base.res_cap->num_dsc; i++) { in dcn20_resource_destruct()
1500 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dcn20_resource_destruct()
1513 for (i = 0; i < pool->base.res_cap->num_opp; i++) { in dcn20_resource_destruct()
1518 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) { in dcn20_resource_destruct()
1525 for (i = 0; i < pool->base.res_cap->num_dwb; i++) { in dcn20_resource_destruct()
1680 if (pool->res_cap->num_dsc == pool->res_cap->num_opp) { in dcn20_acquire_dsc()
1694 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_acquire_dsc()
1708 for (i = 0; i < pool->res_cap->num_dsc; i++) in dcn20_release_dsc()
3349 uint32_t pipe_count = pool->res_cap->num_dwb;
3372 uint32_t pipe_count = pool->res_cap->num_dwb;
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| D | dcn20_hwseq.c | 297 if (opp_id_src0 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
306 if (opp_id_src1 >= dc->res_pool->res_cap->num_opp) { in dcn20_init_blank()
2473 for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { in dcn20_fpga_init_hw()
2508 for (i = 0; i < res_pool->res_cap->num_dwb; i++) in dcn20_fpga_init_hw()
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_resource.c | 844 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_destruct()
1364 pool->base.res_cap = dce110_resource_cap(&ctx->asic_id); in dce110_resource_construct()
1371 pool->base.pipe_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1373 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator; in dce110_resource_construct()
1486 for (i = 0; i < pool->base.res_cap->num_ddc; i++) { in dce110_resource_construct()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 249 const struct resource_caps *res_cap; member
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_i2c_hw.c | 383 if (line < pool->res_cap->num_ddc) in acquire_i2c_hw_engine()
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| /drivers/gpu/drm/amd/display/dc/core/ |
| D | dc_resource.c | 284 const struct resource_caps *caps = pool->res_cap; in resource_construct()
2191 return dc->res_pool->res_cap->num_dsc > 0; in dc_resource_is_dsc_encoding_supported()
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