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Searched refs:rv_funcs (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_pp_smu.c893 funcs->rv_funcs.pp_smu.dm = ctx; in dm_pp_get_funcs()
894 funcs->rv_funcs.set_wm_ranges = pp_rv_set_wm_ranges; in dm_pp_get_funcs()
895 funcs->rv_funcs.set_pme_wa_enable = pp_rv_set_pme_wa_enable; in dm_pp_get_funcs()
896 funcs->rv_funcs.set_display_count = in dm_pp_get_funcs()
898 funcs->rv_funcs.set_min_deep_sleep_dcfclk = in dm_pp_get_funcs()
900 funcs->rv_funcs.set_hard_min_dcfclk_by_freq = in dm_pp_get_funcs()
902 funcs->rv_funcs.set_hard_min_fclk_by_freq = in dm_pp_get_funcs()
/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
Drv1_clk_mgr.c210 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
300 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_enable_pme_wa()
/drivers/gpu/drm/amd/display/dc/
Ddm_pp_smu.h285 struct pp_smu_funcs_rv rv_funcs; member
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_resource.c1532 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c1555 pp = &dc->res_pool->pp_smu->rv_funcs; in dcn_bw_notify_pplib_of_wm_ranges()