| /drivers/net/ethernet/marvell/octeontx2/af/ |
| D | rvu_cgx.c | 27 *otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
32 &rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
38 trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req)); \
46 static u16 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id) in cgxlmac_to_pfmap() argument
48 return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id]; in cgxlmac_to_pfmap()
51 static int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id) in cgxlmac_to_pf() argument
55 pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id); in cgxlmac_to_pf()
69 void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu) in rvu_cgx_pdata() argument
71 if (cgx_id >= rvu->cgx_cnt_max) in rvu_cgx_pdata()
74 return rvu->cgx_idmap[cgx_id]; in rvu_cgx_pdata()
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| D | rvu.c | 28 static int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
30 static void rvu_set_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
32 static void rvu_clear_msix_offset(struct rvu *rvu, struct rvu_pfvf *pfvf,
34 static void __rvu_flr_handler(struct rvu *rvu, u16 pcifunc);
36 static int rvu_mbox_init(struct rvu *rvu, struct mbox_wq_info *mw,
60 static void rvu_setup_hw_capabilities(struct rvu *rvu) in rvu_setup_hw_capabilities() argument
62 struct rvu_hwinfo *hw = rvu->hw; in rvu_setup_hw_capabilities()
70 if (is_rvu_96xx_B0(rvu)) { in rvu_setup_hw_capabilities()
77 if (is_rvu_96xx_A0(rvu)) in rvu_setup_hw_capabilities()
85 int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero) in rvu_poll_reg() argument
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| D | rvu.h | 66 struct rvu *rvu; member
312 struct rvu { struct
370 static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val) in rvu_write64() argument
372 writeq(val, rvu->afreg_base + ((block << 28) | offset)); in rvu_write64()
375 static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset) in rvu_read64() argument
377 return readq(rvu->afreg_base + ((block << 28) | offset)); in rvu_read64()
380 static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val) in rvupf_write64() argument
382 writeq(val, rvu->pfreg_base + offset); in rvupf_write64()
385 static inline u64 rvupf_read64(struct rvu *rvu, u64 offset) in rvupf_read64() argument
387 return readq(rvu->pfreg_base + offset); in rvupf_read64()
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| D | rvu_nix.c | 20 static int rvu_nix_get_bpid(struct rvu *rvu, struct nix_bp_cfg_req *req,
71 bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc) in is_nixlf_attached() argument
73 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); in is_nixlf_attached()
76 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, pcifunc); in is_nixlf_attached()
82 int rvu_get_nixlf_count(struct rvu *rvu) in rvu_get_nixlf_count() argument
87 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NIX, 0); in rvu_get_nixlf_count()
90 block = &rvu->hw->block[blkaddr]; in rvu_get_nixlf_count()
94 int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr) in nix_get_nixlf() argument
96 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, pcifunc); in nix_get_nixlf()
97 struct rvu_hwinfo *hw = rvu->hw; in nix_get_nixlf()
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| D | rvu_npc.c | 34 static void npc_mcam_free_all_entries(struct rvu *rvu, struct npc_mcam *mcam,
36 static void npc_mcam_free_all_counters(struct rvu *rvu, struct npc_mcam *mcam,
39 void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf) in rvu_npc_set_pkind() argument
44 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPC, 0); in rvu_npc_set_pkind()
50 rvu_write64(rvu, blkaddr, NPC_AF_PKINDX_CPI_DEFX(pkind, 0), val); in rvu_npc_set_pkind()
53 int rvu_npc_get_pkind(struct rvu *rvu, u16 pf) in rvu_npc_get_pkind() argument
55 struct npc_pkind *pkind = &rvu->hw->pkind; in rvu_npc_get_pkind()
69 int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool enable) in npc_config_ts_kpuaction() argument
74 pkind = rvu_npc_get_pkind(rvu, pf); in npc_config_ts_kpuaction()
76 dev_err(rvu->dev, "%s: pkind not mapped\n", __func__); in npc_config_ts_kpuaction()
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| D | rvu_npa.c | 18 static int npa_aq_enqueue_wait(struct rvu *rvu, struct rvu_block *block, in npa_aq_enqueue_wait() argument
29 reg = rvu_read64(rvu, block->addr, NPA_AF_AQ_STATUS); in npa_aq_enqueue_wait()
39 rvu_write64(rvu, block->addr, NPA_AF_AQ_DOOR, 1); in npa_aq_enqueue_wait()
55 int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req, in rvu_npa_aq_enq_inst() argument
58 struct rvu_hwinfo *hw = rvu->hw; in rvu_npa_aq_enq_inst()
68 pfvf = rvu_get_pfvf(rvu, pcifunc); in rvu_npa_aq_enq_inst()
72 blkaddr = rvu_get_blkaddr(rvu, BLKTYPE_NPA, pcifunc); in rvu_npa_aq_enq_inst()
79 dev_warn(rvu->dev, "%s: NPA AQ not initialized\n", __func__); in rvu_npa_aq_enq_inst()
83 npalf = rvu_get_lf(rvu, block, pcifunc, 0); in rvu_npa_aq_enq_inst()
152 rc = npa_aq_enqueue_wait(rvu, block, &inst); in rvu_npa_aq_enq_inst()
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| D | rvu_debugfs.c | 112 #define NDC_MAX_BANK(rvu, blk_addr) (rvu_read64(rvu, \ argument
176 static int get_max_column_width(struct rvu *rvu) in get_max_column_width() argument
187 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in get_max_column_width()
188 for (vf = 0; vf <= rvu->hw->total_vfs; vf++) { in get_max_column_width()
194 block = rvu->hw->block[index]; in get_max_column_width()
215 struct rvu *rvu = filp->private_data; in rvu_dbg_rsrc_attach_status() local
233 lf_str_size = get_max_column_width(rvu); in rvu_dbg_rsrc_attach_status()
243 if (strlen(rvu->hw->block[index].name)) { in rvu_dbg_rsrc_attach_status()
246 rvu->hw->block[index].name); in rvu_dbg_rsrc_attach_status()
256 for (pf = 0; pf < rvu->hw->total_pfs; pf++) { in rvu_dbg_rsrc_attach_status()
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| D | ptp.c | 247 int rvu_mbox_handler_ptp_op(struct rvu *rvu, struct ptp_req *req, in rvu_mbox_handler_ptp_op() argument
259 if (!rvu->ptp) in rvu_mbox_handler_ptp_op()
264 err = ptp_adjfine(rvu->ptp, req->scaled_ppm); in rvu_mbox_handler_ptp_op()
267 err = ptp_get_clock(rvu->ptp, &rsp->clk); in rvu_mbox_handler_ptp_op()
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| D | Makefile | 11 octeontx2_af-y := cgx.o rvu.o rvu_cgx.o rvu_npa.o rvu_nix.o \
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| D | rvu_trace.h | 8 #define TRACE_SYSTEM rvu
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