| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | smu7_hwmgr.c | 684 &data->dpm_table.sclk_table, in smu7_reset_dpm_tables()
742 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v0()
745 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count-1].value != in smu7_setup_dpm_tables_v0()
747 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v0()
749 …data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = (i == 0) ? 1 : 0; in smu7_setup_dpm_tables_v0()
750 data->dpm_table.sclk_table.count++; in smu7_setup_dpm_tables_v0()
836 data->dpm_table.sclk_table.count = 0; in smu7_setup_dpm_tables_v1()
838 if (i == 0 || data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count - 1].value != in smu7_setup_dpm_tables_v1()
841 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].value = in smu7_setup_dpm_tables_v1()
844 data->dpm_table.sclk_table.dpm_levels[data->dpm_table.sclk_table.count].enabled = in smu7_setup_dpm_tables_v1()
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| D | process_pptables_v1_0.c | 417 phm_ppt_v1_clock_voltage_dependency_table *sclk_table; in get_sclk_voltage_dependency_table() local
431 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
433 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
436 sclk_table->count = (uint32_t)tonga_table->ucNumEntries; in get_sclk_voltage_dependency_table()
444 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
463 sclk_table = kzalloc(table_size, GFP_KERNEL); in get_sclk_voltage_dependency_table()
465 if (NULL == sclk_table) in get_sclk_voltage_dependency_table()
468 sclk_table->count = (uint32_t)polaris_table->ucNumEntries; in get_sclk_voltage_dependency_table()
476 entries, sclk_table, i); in get_sclk_voltage_dependency_table()
486 *pp_tonga_sclk_dep_table = sclk_table; in get_sclk_voltage_dependency_table()
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| D | smu7_hwmgr.h | 104 struct smu7_single_dpm_table sclk_table; member
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| D | vega10_hwmgr.c | 3390 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_find_dpm_states_clocks_in_dpm_table() local
3398 for (i = 0; i < sclk_table->count; i++) { in vega10_find_dpm_states_clocks_in_dpm_table()
3399 if (sclk == sclk_table->dpm_levels[i].value) in vega10_find_dpm_states_clocks_in_dpm_table()
3403 if (i >= sclk_table->count) { in vega10_find_dpm_states_clocks_in_dpm_table()
3404 if (sclk > sclk_table->dpm_levels[i-1].value) { in vega10_find_dpm_states_clocks_in_dpm_table()
3406 sclk_table->dpm_levels[i-1].value = sclk; in vega10_find_dpm_states_clocks_in_dpm_table()
4625 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_print_clock_levels() local
4646 count = sclk_table->count; in vega10_print_clock_levels()
4649 i, sclk_table->dpm_levels[i].value / 100, in vega10_print_clock_levels()
4926 struct vega10_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table); in vega10_get_sclk_od() local
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| D | smu8_hwmgr.c | 1548 struct phm_clock_voltage_dependency_table *sclk_table = in smu8_print_clock_levels() local
1560 for (i = 0; i < sclk_table->count; i++) in smu8_print_clock_levels()
1562 i, sclk_table->entries[i].clk / 100, in smu8_print_clock_levels()
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| D | vega12_hwmgr.c | 2669 struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2672 int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
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| D | vega20_hwmgr.c | 1471 struct vega20_single_dpm_table *sclk_table = in vega20_get_sclk_od() local
1475 int value = sclk_table->dpm_levels[sclk_table->count - 1].value; in vega20_get_sclk_od()
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| /drivers/gpu/drm/amd/pm/powerplay/smumgr/ |
| D | vegam_smumgr.c | 889 for (i = 0; i < dpm_table->sclk_table.count; i++) { in vegam_populate_all_graphic_levels()
892 dpm_table->sclk_table.dpm_levels[i].value, in vegam_populate_all_graphic_levels()
910 (uint8_t)dpm_table->sclk_table.count; in vegam_populate_all_graphic_levels()
912 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in vegam_populate_all_graphic_levels()
914 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
923 for (i = 0; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
948 for (i = 2; i < dpm_table->sclk_table.count; i++) in vegam_populate_all_graphic_levels()
1288 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in vegam_program_memory_timing_parameters()
1291 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in vegam_program_memory_timing_parameters()
1375 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in vegam_populate_smc_boot_level()
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| D | polaris10_smumgr.c | 1002 for (i = 0; i < dpm_table->sclk_table.count; i++) { in polaris10_populate_all_graphic_levels()
1005 dpm_table->sclk_table.dpm_levels[i].value, in polaris10_populate_all_graphic_levels()
1020 (uint8_t)dpm_table->sclk_table.count; in polaris10_populate_all_graphic_levels()
1022 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in polaris10_populate_all_graphic_levels()
1030 for (i = 0; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1055 for (i = 2; i < dpm_table->sclk_table.count; i++) in polaris10_populate_all_graphic_levels()
1371 for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) { in polaris10_program_memory_timing_parameters()
1374 hw_data->dpm_table.sclk_table.dpm_levels[i].value, in polaris10_program_memory_timing_parameters()
1460 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in polaris10_populate_smc_boot_level()
1520 struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table = in polaris10_populate_clock_stretcher_data_table() local
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| D | tonga_smumgr.c | 710 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
712 dpm_table->sclk_table.dpm_levels[i].value, in tonga_populate_all_graphic_levels()
726 if (dpm_table->sclk_table.count > 1) in tonga_populate_all_graphic_levels()
727 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in tonga_populate_all_graphic_levels()
731 (uint8_t)dpm_table->sclk_table.count; in tonga_populate_all_graphic_levels()
733 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in tonga_populate_all_graphic_levels()
740 for (i = 0; i < dpm_table->sclk_table.count; i++) { in tonga_populate_all_graphic_levels()
770 for (i = 2; i < dpm_table->sclk_table.count; i++) in tonga_populate_all_graphic_levels()
1497 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in tonga_program_memory_timing_parameters()
1500 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in tonga_program_memory_timing_parameters()
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| D | fiji_smumgr.c | 1023 for (i = 0; i < dpm_table->sclk_table.count; i++) { in fiji_populate_all_graphic_levels()
1025 dpm_table->sclk_table.dpm_levels[i].value, in fiji_populate_all_graphic_levels()
1039 levels[dpm_table->sclk_table.count - 1].DisplayWatermark = in fiji_populate_all_graphic_levels()
1043 (uint8_t)dpm_table->sclk_table.count; in fiji_populate_all_graphic_levels()
1045 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in fiji_populate_all_graphic_levels()
1052 for (i = 0; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1077 for (i = 2; i < dpm_table->sclk_table.count; i++) in fiji_populate_all_graphic_levels()
1317 data->dpm_table.sclk_table.dpm_levels[0].value; in fiji_populate_smc_acpi_level()
1533 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in fiji_program_memory_timing_parameters()
1536 data->dpm_table.sclk_table.dpm_levels[i].value, in fiji_program_memory_timing_parameters()
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| D | iceland_smumgr.c | 980 for (i = 0; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
982 dpm_table->sclk_table.dpm_levels[i].value, in iceland_populate_all_graphic_levels()
996 if (dpm_table->sclk_table.count > 1) in iceland_populate_all_graphic_levels()
997 smu_data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark = in iceland_populate_all_graphic_levels()
1001 (uint8_t)dpm_table->sclk_table.count; in iceland_populate_all_graphic_levels()
1003 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in iceland_populate_all_graphic_levels()
1026 for (i = 2; i < dpm_table->sclk_table.count; i++) { in iceland_populate_all_graphic_levels()
1621 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in iceland_program_memory_timing_parameters()
1624 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in iceland_program_memory_timing_parameters()
1657 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in iceland_populate_smc_boot_level()
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| D | ci_smumgr.c | 485 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
487 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
493 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
500 smu_data->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
502 phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
1659 for (i = 0; i < data->dpm_table.sclk_table.count; i++) { in ci_program_memory_timing_parameters()
1662 (hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, in ci_program_memory_timing_parameters()
1695 result = phm_find_boot_level(&(data->dpm_table.sclk_table), in ci_populate_smc_boot_level()
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| /drivers/gpu/drm/radeon/ |
| D | ci_dpm.c | 2540 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2543 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
3274 for (i = 0; i < dpm_table->sclk_table.count; i++) { in ci_populate_all_graphic_levels()
3276 dpm_table->sclk_table.dpm_levels[i].value, in ci_populate_all_graphic_levels()
3283 if (i == (dpm_table->sclk_table.count - 1)) in ci_populate_all_graphic_levels()
3289 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3291 ci_get_dpm_level_enable_mask_value(&dpm_table->sclk_table); in ci_populate_all_graphic_levels()
3449 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3464 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3467 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
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| D | ci_dpm.h | 69 struct ci_single_dpm_table sclk_table; member
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