| /drivers/clk/samsung/ |
| D | clk-pll.c | 109 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
115 sdiv = (pll_con >> PLL2126_SDIV_SHIFT) & PLL2126_SDIV_MASK; in samsung_pll2126_recalc_rate()
118 do_div(fvco, (pdiv + 2) << sdiv); in samsung_pll2126_recalc_rate()
142 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
148 sdiv = (pll_con >> PLL3000_SDIV_SHIFT) & PLL3000_SDIV_MASK; in samsung_pll3000_recalc_rate()
151 do_div(fvco, pdiv << sdiv); in samsung_pll3000_recalc_rate()
179 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
185 sdiv = (pll_con >> PLL35XX_SDIV_SHIFT) & PLL35XX_SDIV_MASK; in samsung_pll35xx_recalc_rate()
188 do_div(fvco, (pdiv << sdiv)); in samsung_pll35xx_recalc_rate()
224 tmp |= rate->sdiv << PLL35XX_SDIV_SHIFT; in samsung_pll35xx_set_rate()
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| D | clk-pll.h | 52 .sdiv = (_s), \
61 .sdiv = (_s), \
70 .sdiv = (_s), \
79 .sdiv = (_s), \
89 .sdiv = (_s), \
99 .sdiv = (_s), \
110 .sdiv = (_s), \
123 unsigned int sdiv; member
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| /drivers/clk/st/ |
| D | clkgen-fsyn.c | 37 unsigned long sdiv; member
60 struct clkgen_field sdiv[QUADFS_MAX_CHAN]; member
105 .sdiv = { CLKGEN_FIELD(0x304, 0xf, 20),
129 .sdiv = { CLKGEN_FIELD(0x2b4, 0xf, 20),
464 u32 sdiv; member
494 CLKGEN_WRITE(fs, sdiv[fs->chan], fs->sdiv); in quadfs_fsynth_program_rate()
563 unsigned long s = (1 << fs->sdiv); in clk_fs660c32_dig_get_rate()
603 fs_tmp.sdiv = si; in clk_fs660c32_get_pe()
613 fs->sdiv = si; in clk_fs660c32_get_pe()
658 fs_tmp.sdiv = fs->sdiv; in clk_fs660c32_dig_get_params()
[all …]
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| /drivers/clk/imx/ |
| D | clk-pll14xx.c | 122 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
128 sdiv = (pll_div & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1416x_recalc_rate()
131 do_div(fvco, pdiv << sdiv); in clk_pll1416x_recalc_rate()
140 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; in clk_pll1443x_recalc_rate() local
148 sdiv = (pll_div_ctl0 & SDIV_MASK) >> SDIV_SHIFT; in clk_pll1443x_recalc_rate()
155 do_div(fvco, pdiv << sdiv); in clk_pll1443x_recalc_rate()
198 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1416x_set_rate()
218 (rate->sdiv << SDIV_SHIFT); in clk_pll1416x_set_rate()
264 tmp |= rate->sdiv << SDIV_SHIFT; in clk_pll1443x_set_rate()
283 (rate->sdiv << SDIV_SHIFT); in clk_pll1443x_set_rate()
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| D | clk.h | 52 unsigned int sdiv; member
184 .sdiv = (_s), \
192 .sdiv = (_s), \
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| /drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
| D | gk104.c | 122 u32 sdiv = (sctl & 0x0000003f) + 2; in read_div() local
123 return (sclk * 2) / sdiv; in read_div()
149 u32 sclk, sdiv; in read_clk() local
155 sdiv = 1; in read_clk()
158 sdiv = 0; in read_clk()
167 sdiv = 1; in read_clk()
169 sdiv = 0; in read_clk()
173 sdiv = 0; in read_clk()
178 if (sdiv) in read_clk()
179 sdiv = ((sctl & 0x00003f00) >> 8) + 2; in read_clk()
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| D | gt215.c | 64 u32 sctl, sdiv, sclk; in read_clk() local
100 sdiv = ((sctl & 0x003f0000) >> 16) + 2; in read_clk()
101 return (sclk * 2) / sdiv; in read_clk()
191 u32 oclk, sclk, sdiv; in gt215_clk_info() local
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
209 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
215 sdiv++; in gt215_clk_info()
216 oclk = (sclk * 2) / sdiv; in gt215_clk_info()
223 if (sdiv > 4) { in gt215_clk_info()
224 info->clk = (((sdiv - 2) << 16) | 0x00003100); in gt215_clk_info()
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| D | gf100.c | 102 u32 sclk, sctl, sdiv = 2; in read_div() local
122 sdiv = (sctl & 0x3f) + 2; in read_div()
126 return (sclk * 2) / sdiv; in read_div()
138 u32 sclk, sdiv; in read_clk() local
145 sdiv = ((sctl & 0x00003f00) >> 8) + 2; in read_clk()
148 sdiv = ((sctl & 0x0000003f) >> 0) + 2; in read_clk()
152 return (sclk * 2) / sdiv; in read_clk()
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