Home
last modified time | relevance | path

Searched refs:slew (Results 1 – 6 of 6) sorted by relevance

/drivers/net/can/cc770/
Dcc770_platform.c115 int slew; in cc770_get_of_node_data() local
124 slew = *prop; in cc770_get_of_node_data()
127 slew = (CLKOUT_SL_MASK >> in cc770_get_of_node_data()
130 if (slew < 0) in cc770_get_of_node_data()
131 slew = 0; in cc770_get_of_node_data()
133 priv->clkout |= (slew << CLKOUT_SL_SHIFT) & in cc770_get_of_node_data()
/drivers/iio/dac/
Dad5755.c516 val = pdata->dac[i].slew.step_size << in ad5755_setup_pdata()
518 val |= pdata->dac[i].slew.rate << in ad5755_setup_pdata()
520 if (pdata->dac[i].slew.enable) in ad5755_setup_pdata()
587 .slew = { \
676 pdata->dac[devnr].slew.enable = tmparray[0]; in ad5755_parse_dt()
678 pdata->dac[devnr].slew.rate = AD5755_SLEW_RATE_64k; in ad5755_parse_dt()
681 pdata->dac[devnr].slew.rate = in ad5755_parse_dt()
691 pdata->dac[devnr].slew.step_size = AD5755_SLEW_STEP_SIZE_1; in ad5755_parse_dt()
694 pdata->dac[devnr].slew.step_size = in ad5755_parse_dt()
704 pdata->dac[devnr].slew.enable = false; in ad5755_parse_dt()
[all …]
/drivers/pinctrl/bcm/
Dpinctrl-ns2-mux.c706 u32 slew) in ns2_pin_set_slew() argument
719 if (slew) in ns2_pin_set_slew()
725 dev_dbg(pctrldev->dev, "pin:%u set slew:%d\n", pin, slew); in ns2_pin_set_slew()
730 u16 *slew) in ns2_pin_get_slew() argument
739 *slew = (val >> pin_data->pin_conf.src_shift) & NS2_PIN_SRC_MASK; in ns2_pin_get_slew()
742 dev_dbg(pctrldev->dev, "pin:%u get slew:%d\n", pin, *slew); in ns2_pin_get_slew()
Dpinctrl-nsp-gpio.c354 static int nsp_gpio_set_slew(struct nsp_gpio *chip, unsigned gpio, u32 slew) in nsp_gpio_set_slew() argument
356 if (slew) in nsp_gpio_set_slew()
/drivers/cpufreq/
Dpmac64-cpufreq.c117 u32 slew, done = 0; in g5_vdnap_switch_volt() local
120 slew = (speed_mode == CPUFREQ_LOW) ? 1 : 0; in g5_vdnap_switch_volt()
122 args.u[0].p = &slew; in g5_vdnap_switch_volt()
/drivers/scsi/aic7xxx/
Daic79xx.reg2712 * Rev A has only a single bit (high bit of field) of slew adjustment.