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Searched refs:soc_mask (Results 1 – 6 of 6) sorted by relevance

/drivers/clk/ti/
Dclkctrl.c515 u16 soc_mask = 0; in _ti_omap4_clkctrl_setup() local
541 soc_mask = CLKF_SOC_DRA72; in _ti_omap4_clkctrl_setup()
543 soc_mask = CLKF_SOC_DRA74; in _ti_omap4_clkctrl_setup()
545 soc_mask = CLKF_SOC_DRA76; in _ti_omap4_clkctrl_setup()
579 soc_mask |= CLKF_SOC_NONSEC; in _ti_omap4_clkctrl_setup()
659 (reg_data->flags & soc_mask) == 0) { in _ti_omap4_clkctrl_setup()
/drivers/gpu/drm/amd/pm/swsmu/smu12/
Drenoir_ppt.c218 uint32_t *soc_mask) in renoir_get_profiling_clk_mask() argument
237 if(soc_mask) in renoir_get_profiling_clk_mask()
238 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1; in renoir_get_profiling_clk_mask()
250 uint32_t mclk_mask, soc_mask; in renoir_get_dpm_ultimate_freq() local
285 &soc_mask); in renoir_get_dpm_ultimate_freq()
306 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max); in renoir_get_dpm_ultimate_freq()
828 uint32_t sclk_mask, mclk_mask, soc_mask; in renoir_set_performance_level() local
896 &soc_mask); in renoir_set_performance_level()
901 renoir_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask); in renoir_set_performance_level()
/drivers/pinctrl/
Dpinctrl-single.c1407 unsigned soc_mask; in pcs_irq_set() local
1413 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1417 mask |= soc_mask; in pcs_irq_set()
1419 mask &= ~soc_mask; in pcs_irq_set()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dvega12_hwmgr.c1698 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega12_get_profiling_clk_mask() argument
1707 *soc_mask = 0; in vega12_get_profiling_clk_mask()
1714 *soc_mask = VEGA12_UMD_PSTATE_SOCCLK_LEVEL; in vega12_get_profiling_clk_mask()
1724 *soc_mask = soc_dpm_table->count - 1; in vega12_get_profiling_clk_mask()
1754 uint32_t soc_mask = 0; in vega12_dpm_force_dpm_level() local
1770 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega12_dpm_force_dpm_level()
Dvega20_hwmgr.c2523 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega20_get_profiling_clk_mask() argument
2532 *soc_mask = 0; in vega20_get_profiling_clk_mask()
2539 *soc_mask = VEGA20_UMD_PSTATE_SOCCLK_LEVEL; in vega20_get_profiling_clk_mask()
2549 *soc_mask = soc_dpm_table->count - 1; in vega20_get_profiling_clk_mask()
2723 uint32_t sclk_mask, mclk_mask, soc_mask; in vega20_dpm_force_dpm_level() local
2742 ret = vega20_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega20_dpm_force_dpm_level()
2747 vega20_force_clock_level(hwmgr, PP_SOCCLK, 1 << soc_mask); in vega20_dpm_force_dpm_level()
Dvega10_hwmgr.c4156 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask) in vega10_get_profiling_clk_mask() argument
4165 *soc_mask = VEGA10_UMD_PSTATE_SOCCLK_LEVEL; in vega10_get_profiling_clk_mask()
4183 *soc_mask = table_info->vdd_dep_on_socclk->count - 1; in vega10_get_profiling_clk_mask()
4277 uint32_t soc_mask = 0; in vega10_dpm_force_dpm_level() local
4280 vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()
4296 ret = vega10_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask); in vega10_dpm_force_dpm_level()