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Searched refs:source_port (Results 1 – 11 of 11) sorted by relevance

/drivers/net/ethernet/mellanox/mlx5/core/
Drdma.c71 misc_parameters.source_port); in mlx5_rdma_enable_roce_steering()
83 MLX5_SET(fte_match_set_misc, misc, source_port, in mlx5_rdma_enable_roce_steering()
87 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_rdma_enable_roce_steering()
Deswitch_offloads_termtbl.c206 misc_parameters.source_port); in mlx5_eswitch_offload_is_uplink_port()
208 misc_parameters.source_port); in mlx5_eswitch_offload_is_uplink_port()
Deswitch_offloads.c281 MLX5_SET(fte_match_set_misc, misc, source_port, attr->in_rep->vport); in mlx5_eswitch_set_rule_source_port()
289 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_eswitch_set_rule_source_port()
787 MLX5_SET(fte_match_set_misc, misc, source_port, esw->manager_vport); in mlx5_eswitch_add_send_to_vport_rule()
791 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_eswitch_add_send_to_vport_rule()
889 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in peer_miss_rules_setup()
916 MLX5_SET(fte_match_set_misc, misc, source_port, vport); in esw_set_peer_miss_rule_source_port()
963 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_ECPF); in esw_add_fdb_peer_miss_rules()
1167 misc_parameters.source_port); in esw_set_flow_group_source_port()
1359 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port); in esw_create_offloads_fdb_tables()
1574 MLX5_SET(fte_match_set_misc, misc, source_port, vport); in mlx5_eswitch_create_vport_rx_rule()
[all …]
Deswitch.c223 MLX5_SET(fte_match_set_misc, mv_misc, source_port, MLX5_VPORT_UPLINK); in __esw_fdb_set_vport_rule()
224 MLX5_SET_TO_ONES(fte_match_set_misc, mc_misc, source_port); in __esw_fdb_set_vport_rule()
392 MLX5_SET_TO_ONES(fte_match_param, match_criteria, misc_parameters.source_port); in esw_create_legacy_fdb_table()
2127 MLX5_SET(fte_match_set_misc, misc, source_port, MLX5_VPORT_UPLINK); in _mlx5_eswitch_set_vepa_locked()
2130 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in _mlx5_eswitch_set_vepa_locked()
/drivers/net/ethernet/mellanox/mlx5/core/diag/
Dfs_tracepoint.c172 PRINT_MASKED_VAL_MISC(u16, source_port, source_port, p, "%u"); in print_misc_parameters_hdrs()
/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_ste.c719 if (mask->misc.source_port && mask->misc.source_port != 0xffff) { in mlx5dr_ste_build_pre_check()
816 spec->source_port = MLX5_GET(fte_match_set_misc, mask, source_port); in dr_ste_copy_mask_misc()
1198 source_port, mask, tcp_sport); in dr_ste_build_eth_l3_ipv4_5_tuple_bit_mask()
1200 source_port, mask, udp_sport); in dr_ste_build_eth_l3_ipv4_5_tuple_bit_mask()
1226 DR_STE_SET_TAG(eth_l3_ipv4_5_tuple, tag, source_port, spec, tcp_sport); in dr_ste_build_eth_l3_ipv4_5_tuple_tag()
1227 DR_STE_SET_TAG(eth_l3_ipv4_5_tuple, tag, source_port, spec, udp_sport); in dr_ste_build_eth_l3_ipv4_5_tuple_tag()
2227 DR_STE_SET_MASK(src_gvmi_qp, bit_mask, source_gvmi, misc_mask, source_port); in dr_ste_build_src_gvmi_qpn_bit_mask()
2258 vport_cap = mlx5dr_get_vport_cap(caps, misc->source_port); in dr_ste_build_src_gvmi_qpn_tag()
2267 misc->source_port = 0; in dr_ste_build_src_gvmi_qpn_tag()
Ddr_rule.c996 if (mask->misc.source_port) { in dr_rule_skip()
997 if (rx && value->misc.source_port != WIRE_PORT) in dr_rule_skip()
1000 if (!rx && value->misc.source_port == WIRE_PORT) in dr_rule_skip()
Dmlx5_ifc_dr.h334 u8 source_port[0x10]; member
Ddr_matcher.c176 return (misc->source_sqn || misc->source_port); in dr_mask_is_gvmi_or_qpn_set()
Ddr_types.h472 u32 source_port:16; member
/drivers/infiniband/hw/mlx5/
Dfs.c893 MLX5_SET(fte_match_set_misc, misc, source_port, rep->vport); in mlx5_ib_set_rule_source_port()
898 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port); in mlx5_ib_set_rule_source_port()