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/drivers/gpu/drm/selftests/
Dtest-drm_rect.c16 struct drm_rect src, dst, clip; in igt_drm_rect_clip_scaled_div_by_zero() local
23 drm_rect_init(&src, 0, 0, 0, 0); in igt_drm_rect_clip_scaled_div_by_zero()
26 visible = drm_rect_clip_scaled(&src, &dst, &clip); in igt_drm_rect_clip_scaled_div_by_zero()
28 FAIL(drm_rect_visible(&src), "Source should not be visible\n"); in igt_drm_rect_clip_scaled_div_by_zero()
30 drm_rect_init(&src, 0, 0, 0, 0); in igt_drm_rect_clip_scaled_div_by_zero()
33 visible = drm_rect_clip_scaled(&src, &dst, &clip); in igt_drm_rect_clip_scaled_div_by_zero()
35 FAIL(drm_rect_visible(&src), "Source should not be visible\n"); in igt_drm_rect_clip_scaled_div_by_zero()
42 struct drm_rect src, dst, clip; in igt_drm_rect_clip_scaled_not_clipped() local
46 drm_rect_init(&src, 0, 0, 1 << 16, 1 << 16); in igt_drm_rect_clip_scaled_not_clipped()
50 visible = drm_rect_clip_scaled(&src, &dst, &clip); in igt_drm_rect_clip_scaled_not_clipped()
[all …]
/drivers/infiniband/core/
Duverbs_marshall.c66 struct rdma_ah_attr *src = ah_attr; in ib_copy_ah_attr_to_user() local
74 src = &conv_ah; in ib_copy_ah_attr_to_user()
76 dst->dlid = rdma_ah_get_dlid(src); in ib_copy_ah_attr_to_user()
77 dst->sl = rdma_ah_get_sl(src); in ib_copy_ah_attr_to_user()
78 dst->src_path_bits = rdma_ah_get_path_bits(src); in ib_copy_ah_attr_to_user()
79 dst->static_rate = rdma_ah_get_static_rate(src); in ib_copy_ah_attr_to_user()
80 dst->is_global = rdma_ah_get_ah_flags(src) & in ib_copy_ah_attr_to_user()
83 const struct ib_global_route *grh = rdma_ah_read_grh(src); in ib_copy_ah_attr_to_user()
91 dst->port_num = rdma_ah_get_port_num(src); in ib_copy_ah_attr_to_user()
98 struct ib_qp_attr *src) in ib_copy_qp_attr_to_user() argument
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/drivers/phy/
Dphy-xgene.c85 #define SATA_MEM_RESET_RD(src) (((src) & 0x00000020) >> 5) argument
94 #define REGSPEC_CFG_I_TX_WORDMODE0_SET(dst, src) \ argument
95 (((dst) & ~0x00070000) | (((u32) (src) << 16) & 0x00070000))
96 #define REGSPEC_CFG_I_RX_WORDMODE0_SET(dst, src) \ argument
97 (((dst) & ~0x00e00000) | (((u32) (src) << 21) & 0x00e00000))
99 #define REGSPEC_CFG_I_CUSTOMER_PIN_MODE0_SET(dst, src) \ argument
100 (((dst) & ~0x00007fff) | (((u32) (src)) & 0x00007fff))
102 #define CFG_I_SPD_SEL_CDR_OVR1_SET(dst, src) \ argument
103 (((dst) & ~0x0000000f) | (((u32) (src)) & 0x0000000f))
109 #define CFG_IND_ADDR_SET(dst, src) \ argument
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/drivers/gpu/drm/omapdrm/displays/
Dpanel-dsi-cm.c43 struct omap_dss_device *src; member
144 struct omap_dss_device *src = ddata->src; in dsicm_dcs_read_1() local
148 r = src->ops->dsi.dcs_read(src, ddata->channel, dcs_cmd, buf, 1); in dsicm_dcs_read_1()
160 struct omap_dss_device *src = ddata->src; in dsicm_dcs_write_0() local
162 return src->ops->dsi.dcs_write(src, ddata->channel, &dcs_cmd, 1); in dsicm_dcs_write_0()
167 struct omap_dss_device *src = ddata->src; in dsicm_dcs_write_1() local
170 return src->ops->dsi.dcs_write(src, ddata->channel, buf, 2); in dsicm_dcs_write_1()
176 struct omap_dss_device *src = ddata->src; in dsicm_sleep_in() local
183 r = src->ops->dsi.dcs_write_nosync(src, ddata->channel, &cmd, 1); in dsicm_sleep_in()
231 struct omap_dss_device *src = ddata->src; in dsicm_set_update_window() local
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/drivers/video/fbdev/core/
Dsyscopyarea.c29 const unsigned long *src, unsigned src_idx, int bits, unsigned n) in bitcpy() argument
44 *dst = comp(*src, *dst, first); in bitcpy()
49 *dst = comp(*src, *dst, first); in bitcpy()
51 src++; in bitcpy()
58 *dst++ = *src++; in bitcpy()
59 *dst++ = *src++; in bitcpy()
60 *dst++ = *src++; in bitcpy()
61 *dst++ = *src++; in bitcpy()
62 *dst++ = *src++; in bitcpy()
63 *dst++ = *src++; in bitcpy()
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Dcfbcopyarea.c47 const unsigned long __iomem *src, unsigned src_idx, int bits, in bitcpy() argument
59 (char *)src + ((src_idx & (bits - 1))) / 8, n / 8); in bitcpy()
73 FB_WRITEL( comp( FB_READL(src), FB_READL(dst), first), dst); in bitcpy()
79 FB_WRITEL( comp( FB_READL(src), FB_READL(dst), first), dst); in bitcpy()
81 src++; in bitcpy()
88 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
89 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
90 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
91 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
92 FB_WRITEL(FB_READL(src++), dst++); in bitcpy()
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/drivers/infiniband/hw/vmw_pvrdma/
Dpvrdma_misc.c224 void pvrdma_qp_cap_to_ib(struct ib_qp_cap *dst, const struct pvrdma_qp_cap *src) in pvrdma_qp_cap_to_ib() argument
226 dst->max_send_wr = src->max_send_wr; in pvrdma_qp_cap_to_ib()
227 dst->max_recv_wr = src->max_recv_wr; in pvrdma_qp_cap_to_ib()
228 dst->max_send_sge = src->max_send_sge; in pvrdma_qp_cap_to_ib()
229 dst->max_recv_sge = src->max_recv_sge; in pvrdma_qp_cap_to_ib()
230 dst->max_inline_data = src->max_inline_data; in pvrdma_qp_cap_to_ib()
233 void ib_qp_cap_to_pvrdma(struct pvrdma_qp_cap *dst, const struct ib_qp_cap *src) in ib_qp_cap_to_pvrdma() argument
235 dst->max_send_wr = src->max_send_wr; in ib_qp_cap_to_pvrdma()
236 dst->max_recv_wr = src->max_recv_wr; in ib_qp_cap_to_pvrdma()
237 dst->max_send_sge = src->max_send_sge; in ib_qp_cap_to_pvrdma()
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/drivers/gpu/drm/nouveau/nvkm/subdev/
DKbuild2 include $(src)/nvkm/subdev/acr/Kbuild
3 include $(src)/nvkm/subdev/bar/Kbuild
4 include $(src)/nvkm/subdev/bios/Kbuild
5 include $(src)/nvkm/subdev/bus/Kbuild
6 include $(src)/nvkm/subdev/clk/Kbuild
7 include $(src)/nvkm/subdev/devinit/Kbuild
8 include $(src)/nvkm/subdev/fault/Kbuild
9 include $(src)/nvkm/subdev/fb/Kbuild
10 include $(src)/nvkm/subdev/fuse/Kbuild
11 include $(src)/nvkm/subdev/gpio/Kbuild
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/drivers/staging/comedi/drivers/
Dni_routes.c50 #define RVi(table, src, dest) ((table)[(dest) * NI_NUM_NAMES + (src)]) argument
163 const int src = R->src[j]; in ni_count_valid_routes() local
167 if (RVi(rv, B(src), B(dest))) in ni_count_valid_routes()
171 (RVi(rv, B(src), B(NI_RGOUT0)) || in ni_count_valid_routes()
172 RVi(rv, B(src), B(NI_RTSI_BRD(0))) || in ni_count_valid_routes()
173 RVi(rv, B(src), B(NI_RTSI_BRD(1))) || in ni_count_valid_routes()
174 RVi(rv, B(src), B(NI_RTSI_BRD(2))) || in ni_count_valid_routes()
175 RVi(rv, B(src), B(NI_RTSI_BRD(3))))) { in ni_count_valid_routes()
217 const int src = R->src[j]; in ni_get_valid_routes() local
222 if (RVi(rv, B(src), B(dest))) in ni_get_valid_routes()
[all …]
Dni_routes.h42 int *src; member
101 bool ni_route_set_has_source(const struct ni_route_set *routes, const int src);
133 s8 ni_route_to_register(const int src, const int dest,
151 s8 ni_lookup_route_register(int src, int dest,
163 static inline bool route_is_valid(const int src, const int dest, in route_is_valid() argument
166 return ni_route_to_register(src, dest, tables) >= 0; in route_is_valid()
266 static inline s8 ni_get_reg_value_roffs(int src, const int dest, in ni_get_reg_value_roffs() argument
270 if (src < NI_NAMES_BASE) { in ni_get_reg_value_roffs()
271 src += direct_reg_offset; in ni_get_reg_value_roffs()
276 if (route_register_is_valid(src, dest, tables)) in ni_get_reg_value_roffs()
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/drivers/staging/comedi/drivers/ni_routing/ni_device_routes/
Dpxi-6030e.c36 .src = (int[]){
43 .src = (int[]){
50 .src = (int[]){
57 .src = (int[]){
64 .src = (int[]){
71 .src = (int[]){
78 .src = (int[]){
85 .src = (int[]){
92 .src = (int[]){
99 .src = (int[]){
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Dpci-6070e.c36 .src = (int[]){
43 .src = (int[]){
50 .src = (int[]){
57 .src = (int[]){
64 .src = (int[]){
71 .src = (int[]){
78 .src = (int[]){
85 .src = (int[]){
92 .src = (int[]){
99 .src = (int[]){
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Dpxi-6733.c36 .src = (int[]){
43 .src = (int[]){
50 .src = (int[]){
57 .src = (int[]){
64 .src = (int[]){
71 .src = (int[]){
78 .src = (int[]){
90 .src = (int[]){
102 .src = (int[]){
114 .src = (int[]){
[all …]
Dpci-6733.c36 .src = (int[]){
43 .src = (int[]){
50 .src = (int[]){
57 .src = (int[]){
64 .src = (int[]){
71 .src = (int[]){
78 .src = (int[]){
90 .src = (int[]){
102 .src = (int[]){
114 .src = (int[]){
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Dpci-6713.c36 .src = (int[]){
43 .src = (int[]){
50 .src = (int[]){
57 .src = (int[]){
64 .src = (int[]){
71 .src = (int[]){
78 .src = (int[]){
90 .src = (int[]){
102 .src = (int[]){
114 .src = (int[]){
[all …]
Dpci-6723.c36 .src = (int[]){
43 .src = (int[]){
50 .src = (int[]){
57 .src = (int[]){
64 .src = (int[]){
71 .src = (int[]){
78 .src = (int[]){
90 .src = (int[]){
102 .src = (int[]){
114 .src = (int[]){
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/drivers/gpu/drm/nouveau/nvkm/engine/
DKbuild5 include $(src)/nvkm/engine/bsp/Kbuild
6 include $(src)/nvkm/engine/ce/Kbuild
7 include $(src)/nvkm/engine/cipher/Kbuild
8 include $(src)/nvkm/engine/device/Kbuild
9 include $(src)/nvkm/engine/disp/Kbuild
10 include $(src)/nvkm/engine/dma/Kbuild
11 include $(src)/nvkm/engine/fifo/Kbuild
12 include $(src)/nvkm/engine/gr/Kbuild
13 include $(src)/nvkm/engine/mpeg/Kbuild
14 include $(src)/nvkm/engine/msenc/Kbuild
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/drivers/staging/media/allegro-dvt/
Dallegro-mail.c249 u32 *src) in allegro_decode_config_blob() argument
254 param->num_ref_idx_l0 = FIELD_GET(GENMASK(7, 4), src[9]); in allegro_decode_config_blob()
255 param->num_ref_idx_l1 = FIELD_GET(GENMASK(11, 8), src[9]); in allegro_decode_config_blob()
351 allegro_dec_init(struct mcu_msg_init_response *msg, u32 *src) in allegro_dec_init() argument
355 msg->reserved0 = src[i++]; in allegro_dec_init()
357 return i * sizeof(*src); in allegro_dec_init()
362 u32 *src) in allegro_dec_create_channel() argument
367 msg->channel_id = src[i++]; in allegro_dec_create_channel()
368 msg->user_id = src[i++]; in allegro_dec_create_channel()
374 msg->options = src[i++]; in allegro_dec_create_channel()
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/drivers/infiniband/ulp/opa_vnic/
Dopa_vnic_vema_iface.c89 u64 *src; in opa_vnic_get_summary_counters() local
111 for (dst = &cntrs->tx_unicast, src = &vstats.tx_grp.unicast; in opa_vnic_get_summary_counters()
112 dst < &cntrs->reserved[0]; dst++, src++) { in opa_vnic_get_summary_counters()
113 *dst = cpu_to_be64(*src); in opa_vnic_get_summary_counters()
164 struct __opa_vesw_info *src = &adapter->info.vesw; in opa_vnic_get_vesw_info() local
167 info->fabric_id = cpu_to_be16(src->fabric_id); in opa_vnic_get_vesw_info()
168 info->vesw_id = cpu_to_be16(src->vesw_id); in opa_vnic_get_vesw_info()
169 memcpy(info->rsvd0, src->rsvd0, ARRAY_SIZE(src->rsvd0)); in opa_vnic_get_vesw_info()
170 info->def_port_mask = cpu_to_be16(src->def_port_mask); in opa_vnic_get_vesw_info()
171 memcpy(info->rsvd1, src->rsvd1, ARRAY_SIZE(src->rsvd1)); in opa_vnic_get_vesw_info()
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/drivers/gpu/drm/i915/
Di915_memcpy.c38 static void __memcpy_ntdqa(void *dst, const void *src, unsigned long len) in __memcpy_ntdqa() argument
51 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqa()
52 src += 64; in __memcpy_ntdqa()
59 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqa()
60 src += 16; in __memcpy_ntdqa()
67 static void __memcpy_ntdqu(void *dst, const void *src, unsigned long len) in __memcpy_ntdqu() argument
80 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqu()
81 src += 64; in __memcpy_ntdqu()
88 :: "r" (src), "r" (dst) : "memory"); in __memcpy_ntdqu()
89 src += 16; in __memcpy_ntdqu()
[all …]
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_irq.c122 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_disable_all() local
124 if (!src || !src->funcs->set || !src->num_types) in amdgpu_irq_disable_all()
127 for (k = 0; k < src->num_types; ++k) { in amdgpu_irq_disable_all()
128 atomic_set(&src->enabled_types[k], 0); in amdgpu_irq_disable_all()
129 r = src->funcs->set(adev, src, k, in amdgpu_irq_disable_all()
326 struct amdgpu_irq_src *src = adev->irq.client[i].sources[j]; in amdgpu_irq_fini() local
328 if (!src) in amdgpu_irq_fini()
331 kfree(src->enabled_types); in amdgpu_irq_fini()
332 src->enabled_types = NULL; in amdgpu_irq_fini()
333 if (src->data) { in amdgpu_irq_fini()
[all …]
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_blit.c38 (const _type * dst, const _type * src, size_t size)\
43 if (*dst++ != *src++) \
59 const _type * dst, const _type * src, size_t size) \
62 if (*--dst != *--src) \
108 if (spill && spill == SPILL(src, _type) && \
111 diff_offs = vmw_find_first_diff_u8(dst, src, spill); \
116 src += spill; \
121 if (!spill && !SPILL(src, _type)) { \
125 ((_type *) dst, (_type *) src, to_copy); \
130 src += diff_offs; \
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/drivers/misc/vmw_vmci/
Dvmci_route.c20 int vmci_route(struct vmci_handle *src, in vmci_route() argument
64 if (VMCI_HOST_CONTEXT_ID == src->context) in vmci_route()
75 if (VMCI_INVALID_ID == src->context && in vmci_route()
76 VMCI_INVALID_ID != src->resource) in vmci_route()
77 src->context = vmci_get_context_id(); in vmci_route()
94 if (src->context == VMCI_HYPERVISOR_CONTEXT_ID) { in vmci_route()
113 if (VMCI_INVALID_ID == src->context) in vmci_route()
114 src->context = vmci_get_context_id(); in vmci_route()
130 if (VMCI_INVALID_ID == src->context) { in vmci_route()
139 src->context = VMCI_HOST_CONTEXT_ID; in vmci_route()
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/drivers/block/xen-blkback/
Dcommon.h401 struct blkif_x86_32_request *src) in blkif_get_x86_32_req() argument
404 dst->operation = READ_ONCE(src->operation); in blkif_get_x86_32_req()
410 dst->u.rw.nr_segments = src->u.rw.nr_segments; in blkif_get_x86_32_req()
411 dst->u.rw.handle = src->u.rw.handle; in blkif_get_x86_32_req()
412 dst->u.rw.id = src->u.rw.id; in blkif_get_x86_32_req()
413 dst->u.rw.sector_number = src->u.rw.sector_number; in blkif_get_x86_32_req()
418 dst->u.rw.seg[i] = src->u.rw.seg[i]; in blkif_get_x86_32_req()
421 dst->u.discard.flag = src->u.discard.flag; in blkif_get_x86_32_req()
422 dst->u.discard.id = src->u.discard.id; in blkif_get_x86_32_req()
423 dst->u.discard.sector_number = src->u.discard.sector_number; in blkif_get_x86_32_req()
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/drivers/crypto/ccp/
Dccp-ops.c342 static void ccp_prepare_data(struct ccp_data *src, struct ccp_data *dst, in ccp_prepare_data() argument
353 sg_src_len = sg_dma_len(src->sg_wa.dma_sg) - src->sg_wa.sg_used; in ccp_prepare_data()
354 sg_src_len = min_t(u64, src->sg_wa.bytes_left, sg_src_len); in ccp_prepare_data()
358 sg_dst_len = min_t(u64, src->sg_wa.bytes_left, sg_dst_len); in ccp_prepare_data()
377 int cp_len = ccp_fill_queue_buf(src); in ccp_prepare_data()
380 op->src.u.dma.address = src->dm_wa.dma.address; in ccp_prepare_data()
381 op->src.u.dma.offset = 0; in ccp_prepare_data()
382 op->src.u.dma.length = (blocksize_op) ? block_size : cp_len; in ccp_prepare_data()
387 op->src.u.dma.address = sg_dma_address(src->sg_wa.dma_sg); in ccp_prepare_data()
388 op->src.u.dma.offset = src->sg_wa.sg_used; in ccp_prepare_data()
[all …]

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