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Searched refs:taps (Results 1 – 25 of 27) sorted by relevance

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/drivers/misc/echo/
Dfir.h42 int taps; member
54 int taps; member
65 int taps; member
72 const int16_t *coeffs, int taps) in fir16_create() argument
74 fir->taps = taps; in fir16_create()
75 fir->curr_pos = taps - 1; in fir16_create()
77 fir->history = kcalloc(taps, sizeof(int16_t), GFP_KERNEL); in fir16_create()
83 memset(fir->history, 0, fir->taps * sizeof(int16_t)); in fir16_flush()
101 offset1 = fir->taps - offset2; in fir16()
103 for (i = fir->taps - 1; i >= offset1; i--) in fir16()
[all …]
Decho.c123 offset1 = ec->taps - offset2; in lms_adapt_bg()
125 for (i = ec->taps - 1; i >= offset1; i--) { in lms_adapt_bg()
153 ec->taps = len; in oslec_create()
155 ec->curr_pos = ec->taps - 1; in oslec_create()
158 kcalloc(ec->taps, sizeof(int16_t), GFP_KERNEL); in oslec_create()
163 kcalloc(ec->taps, sizeof(int16_t), GFP_KERNEL); in oslec_create()
167 history = fir16_create(&ec->fir_state, ec->fir_taps16[0], ec->taps); in oslec_create()
170 history = fir16_create(&ec->fir_state_bg, ec->fir_taps16[1], ec->taps); in oslec_create()
180 ec->snapshot = kcalloc(ec->taps, sizeof(int16_t), GFP_KERNEL); in oslec_create()
244 ec->fir_state.curr_pos = ec->taps - 1; in oslec_flush()
[all …]
Decho.h125 int taps; member
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c233 static const uint16_t *dpp1_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) in dpp1_dscl_get_filter_coeffs_64p() argument
235 if (taps == 8) in dpp1_dscl_get_filter_coeffs_64p()
237 else if (taps == 7) in dpp1_dscl_get_filter_coeffs_64p()
239 else if (taps == 6) in dpp1_dscl_get_filter_coeffs_64p()
241 else if (taps == 5) in dpp1_dscl_get_filter_coeffs_64p()
243 else if (taps == 4) in dpp1_dscl_get_filter_coeffs_64p()
245 else if (taps == 3) in dpp1_dscl_get_filter_coeffs_64p()
247 else if (taps == 2) in dpp1_dscl_get_filter_coeffs_64p()
249 else if (taps == 1) in dpp1_dscl_get_filter_coeffs_64p()
260 uint32_t taps, in dpp1_dscl_set_scaler_filter() argument
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Ddcn10_dpp.c163 scl_data->taps.h_taps = 4; in dpp1_get_optimal_number_of_taps()
165 scl_data->taps.h_taps = in_taps->h_taps; in dpp1_get_optimal_number_of_taps()
167 scl_data->taps.v_taps = 4; in dpp1_get_optimal_number_of_taps()
169 scl_data->taps.v_taps = in_taps->v_taps; in dpp1_get_optimal_number_of_taps()
171 scl_data->taps.v_taps_c = 2; in dpp1_get_optimal_number_of_taps()
173 scl_data->taps.v_taps_c = in_taps->v_taps_c; in dpp1_get_optimal_number_of_taps()
175 scl_data->taps.h_taps_c = 2; in dpp1_get_optimal_number_of_taps()
178 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1; in dpp1_get_optimal_number_of_taps()
180 scl_data->taps.h_taps_c = in_taps->h_taps_c; in dpp1_get_optimal_number_of_taps()
184 scl_data->taps.h_taps = 1; in dpp1_get_optimal_number_of_taps()
[all …]
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c122 if (data->taps.h_taps + data->taps.v_taps <= 2) { in setup_scaling_configuration()
132 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in setup_scaling_configuration()
133 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in setup_scaling_configuration()
156 if (data->taps.h_taps + data->taps.v_taps <= 2) { in dce60_setup_scaling_configuration()
165 SCL_H_NUM_OF_TAPS, data->taps.h_taps - 1, in dce60_setup_scaling_configuration()
166 SCL_V_NUM_OF_TAPS, data->taps.v_taps - 1); in dce60_setup_scaling_configuration()
209 int taps, in program_multi_taps_filter() argument
215 int taps_pairs = (taps + 1) / 2; in program_multi_taps_filter()
242 if (taps % 2 && pair == taps_pairs - 1) in program_multi_taps_filter()
294 dc_fixpt_from_int(data->taps.h_taps + 1)), in calculate_inits()
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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_dwb_scl.c649 static const uint16_t *wbscl_get_filter_coeffs_16p(int taps, struct fixed31_32 ratio) in wbscl_get_filter_coeffs_16p() argument
651 if (taps == 12) in wbscl_get_filter_coeffs_16p()
653 else if (taps == 11) in wbscl_get_filter_coeffs_16p()
655 else if (taps == 10) in wbscl_get_filter_coeffs_16p()
657 else if (taps == 9) in wbscl_get_filter_coeffs_16p()
659 else if (taps == 8) in wbscl_get_filter_coeffs_16p()
661 else if (taps == 7) in wbscl_get_filter_coeffs_16p()
663 else if (taps == 6) in wbscl_get_filter_coeffs_16p()
665 else if (taps == 5) in wbscl_get_filter_coeffs_16p()
667 else if (taps == 4) in wbscl_get_filter_coeffs_16p()
[all …]
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_transform_v.c167 set_reg_field_value(value, data->taps.h_taps - 1, in setup_scaling_configuration()
169 set_reg_field_value(value, data->taps.v_taps - 1, in setup_scaling_configuration()
171 set_reg_field_value(value, data->taps.h_taps_c - 1, in setup_scaling_configuration()
173 set_reg_field_value(value, data->taps.v_taps_c - 1, in setup_scaling_configuration()
178 if (data->taps.h_taps + data->taps.v_taps > 2) { in setup_scaling_configuration()
187 if (data->taps.h_taps_c + data->taps.v_taps_c > 2) { in setup_scaling_configuration()
287 int taps, in program_multi_taps_filter() argument
294 int taps_pairs = (taps + 1) / 2; in program_multi_taps_filter()
343 if (taps % 2 && pair == taps_pairs - 1) { in program_multi_taps_filter()
491 static const uint16_t *get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) in get_filter_coeffs_64p() argument
[all …]
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c407 scl_data->taps.h_taps = min(2 * dc_fixpt_ceil(scl_data->ratios.horz), 8); in dpp3_get_optimal_number_of_taps()
409 scl_data->taps.h_taps = 4; in dpp3_get_optimal_number_of_taps()
411 scl_data->taps.h_taps = in_taps->h_taps; in dpp3_get_optimal_number_of_taps()
414 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
416 scl_data->taps.v_taps = 4; in dpp3_get_optimal_number_of_taps()
418 scl_data->taps.v_taps = in_taps->v_taps; in dpp3_get_optimal_number_of_taps()
421 scl_data->taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert_c, 2)), 8); in dpp3_get_optimal_number_of_taps()
423 scl_data->taps.v_taps_c = 4; in dpp3_get_optimal_number_of_taps()
425 scl_data->taps.v_taps_c = in_taps->v_taps_c; in dpp3_get_optimal_number_of_taps()
428 scl_data->taps.h_taps_c = min(2 * dc_fixpt_ceil(scl_data->ratios.horz_c), 8); in dpp3_get_optimal_number_of_taps()
[all …]
/drivers/mmc/host/
Drenesas_sdhi_core.c596 if (!test_bit(i, priv->taps)) in renesas_sdhi_select_tuning()
597 clear_bit(i + offset, priv->taps); in renesas_sdhi_select_tuning()
607 if (bitmap_full(priv->taps, taps_size)) { in renesas_sdhi_select_tuning()
611 bitmap = priv->taps; in renesas_sdhi_select_tuning()
654 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { in renesas_sdhi_execute_tuning()
660 bitmap_zero(priv->taps, priv->tap_num * 2); in renesas_sdhi_execute_tuning()
671 set_bit(i, priv->taps); in renesas_sdhi_execute_tuning()
1079 const struct renesas_sdhi_scc *taps = of_data->taps; in renesas_sdhi_probe() local
1084 if (taps[i].clk_rate == 0 || in renesas_sdhi_probe()
1085 taps[i].clk_rate == host->mmc->f_max) { in renesas_sdhi_probe()
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Drenesas_sdhi.h30 struct renesas_sdhi_scc *taps; member
68 DECLARE_BITMAP(taps, BITS_PER_LONG);
Drenesas_sdhi_internal_dmac.c97 .taps = rcar_gen3_scc_taps,
112 .taps = rcar_gen3_scc_taps,
Drenesas_sdhi_sys_dmac.c66 .taps = rcar_gen2_scc_taps,
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c889 int taps, in adjust_vp_and_init_for_seamless_clip() argument
911 if (int_part < taps) { in adjust_vp_and_init_for_seamless_clip()
912 int int_adj = *vp_offset >= (taps - int_part) ? in adjust_vp_and_init_for_seamless_clip()
913 (taps - int_part) : *vp_offset; in adjust_vp_and_init_for_seamless_clip()
917 } else if (int_part > taps) { in adjust_vp_and_init_for_seamless_clip()
918 *vp_offset += int_part - taps; in adjust_vp_and_init_for_seamless_clip()
919 *vp_size -= int_part - taps; in adjust_vp_and_init_for_seamless_clip()
920 int_part = taps; in adjust_vp_and_init_for_seamless_clip()
950 if (int_part < taps) { in adjust_vp_and_init_for_seamless_clip()
951 int int_adj = end_offset >= (taps - int_part) ? in adjust_vp_and_init_for_seamless_clip()
[all …]
/drivers/net/
Dtap.c155 rcu_assign_pointer(tap->taps[tap->numvtaps], q); in tap_enable_queue()
172 rcu_assign_pointer(tap->taps[tap->numvtaps], q); in tap_set_queue()
201 nq = rtnl_dereference(tap->taps[tap->numvtaps - 1]); in tap_disable_queue()
204 rcu_assign_pointer(tap->taps[index], nq); in tap_disable_queue()
205 RCU_INIT_POINTER(tap->taps[tap->numvtaps - 1], NULL); in tap_disable_queue()
273 queue = rcu_dereference(tap->taps[rxq % numvtaps]); in tap_get_queue()
283 queue = rcu_dereference(tap->taps[rxq]); in tap_get_queue()
288 queue = rcu_dereference(tap->taps[0]); in tap_get_queue()
/drivers/gpu/drm/imx/dcss/
Ddcss-scaler.c178 int taps; in dcss_scaler_gaussian_filter() local
187 taps = use_5_taps ? PSC_NUM_TAPS_RGBA : PSC_NUM_TAPS; in dcss_scaler_gaussian_filter()
188 mid = (PSC_NUM_PHASES * taps) / 2 - 1; in dcss_scaler_gaussian_filter()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c398 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
404 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
405 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; in pipe_ctx_to_e2e_pipe_params()
406 input->scale_taps.htaps_c = pipe->plane_res.scl_data.taps.h_taps_c; in pipe_ctx_to_e2e_pipe_params()
1030 v->override_hta_ps[input_idx] = pipe->plane_res.scl_data.taps.h_taps; in dcn_validate_bandwidth()
1031 v->override_vta_ps[input_idx] = pipe->plane_res.scl_data.taps.v_taps; in dcn_validate_bandwidth()
1032 v->override_hta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.h_taps_c; in dcn_validate_bandwidth()
1033 v->override_vta_pschroma[input_idx] = pipe->plane_res.scl_data.taps.v_taps_c; in dcn_validate_bandwidth()
Ddce_calcs.c2802 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2803 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2857 …_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.h_taps); in populate_initial_data()
2858 …_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.v_taps); in populate_initial_data()
2904 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2905 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtransform.h173 struct scaling_taps taps; member
/drivers/gpu/drm/amd/display/dc/dml/
Ddisplay_mode_vba.c385 scaler_taps_st *taps = &pipes[j].pipe.scale_taps; in fetch_pipe_params() local
428 mode_lib->vba.htaps[mode_lib->vba.NumberOfActivePlanes] = taps->htaps; in fetch_pipe_params()
429 mode_lib->vba.vtaps[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps; in fetch_pipe_params()
430 mode_lib->vba.HTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->htaps_c; in fetch_pipe_params()
431 mode_lib->vba.VTAPsChroma[mode_lib->vba.NumberOfActivePlanes] = taps->vtaps_c; in fetch_pipe_params()
/drivers/staging/media/ipu3/
Dipu3-css-params.c44 imgu_css_scaler_setup_lut(unsigned int taps, unsigned int input_width, in imgu_css_scaler_setup_lut() argument
57 for (tap = 0; tap < taps; tap++) in imgu_css_scaler_setup_lut()
74 for (tap = 0; tap < taps; tap++) { in imgu_css_scaler_setup_lut()
77 ((tap * (coeffs_size / taps)) + phase) - 1]; in imgu_css_scaler_setup_lut()
92 phase_sum_left = (taps / 2 * IMGU_SCALER_PHASES * in imgu_css_scaler_setup_lut()
95 phase_sum_right = (taps / 2 * IMGU_SCALER_PHASES * in imgu_css_scaler_setup_lut()
106 info->crop_left = taps - 1; in imgu_css_scaler_setup_lut()
107 info->crop_top = taps - 1; in imgu_css_scaler_setup_lut()
/drivers/gpu/drm/amd/display/dc/dml/dcn20/
Ddisplay_rq_dlg_calc_20.c800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20_rq_dlg_get_dlg_params() local
984 htaps_l = taps->htaps; in dml20_rq_dlg_get_dlg_params()
985 htaps_c = taps->htaps_c; in dml20_rq_dlg_get_dlg_params()
Ddisplay_rq_dlg_calc_20v2.c800 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml20v2_rq_dlg_get_dlg_params() local
985 htaps_l = taps->htaps; in dml20v2_rq_dlg_get_dlg_params()
986 htaps_c = taps->htaps_c; in dml20v2_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn21/
Ddisplay_rq_dlg_calc_21.c846 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params() local
1036 htaps_l = taps->htaps; in dml_rq_dlg_get_dlg_params()
1037 htaps_c = taps->htaps_c; in dml_rq_dlg_get_dlg_params()
/drivers/gpu/drm/amd/display/dc/dml/dcn30/
Ddisplay_rq_dlg_calc_30.c1000 const scaler_taps_st *taps = &e2e_pipe_param[pipe_idx].pipe.scale_taps; in dml_rq_dlg_get_dlg_params() local
1185 htaps_l = taps->htaps; in dml_rq_dlg_get_dlg_params()
1186 htaps_c = taps->htaps_c; in dml_rq_dlg_get_dlg_params()

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