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Searched refs:tg (Results 1 – 25 of 52) sorted by relevance

123

/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_timing_generator.h117 #define DCE110TG_FROM_TG(tg)\ argument
118 container_of(tg, struct dce110_timing_generator, base)
121 struct dce110_timing_generator *tg,
128 struct timing_generator *tg,
136 struct timing_generator *tg,
140 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
141 bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
144 struct timing_generator *tg,
151 struct timing_generator *tg);
154 struct timing_generator *tg,
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Ddce110_timing_generator.c66 struct timing_generator *tg, in dce110_timing_generator_apply_front_porch_workaround() argument
92 struct timing_generator *tg) in dce110_timing_generator_is_in_vertical_blank() argument
97 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_is_in_vertical_blank()
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
106 struct timing_generator *tg, in dce110_timing_generator_set_early_control() argument
110 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_set_early_control()
113 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
116 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control()
123 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_enable_crtc() argument
127 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_enable_crtc()
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Ddce110_timing_generator_v.c42 tg->ctx->logger
53 static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_enable_crtc() argument
65 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
70 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
75 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
81 static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_disable_crtc() argument
85 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
91 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
100 static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) in dce110_timing_generator_v_blank_crtc() argument
103 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
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Ddce110_hw_sequencer.c665 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dce110_enable_stream() local
688 tg->funcs->set_early_control(tg, early_control); in dce110_enable_stream()
1258 pipe_ctx->stream_res.tg->inst + 1); in build_audio_output()
1270 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in get_surface_visual_confirm_color()
1325 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in program_scaler()
1334 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in program_scaler()
1335 pipe_ctx->stream_res.tg, in program_scaler()
1358 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_enable_stream_timing()
1359 pipe_ctx->stream_res.tg, in dce110_enable_stream_timing()
1366 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); in dce110_enable_stream_timing()
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/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtiming_generator.h150 bool (*validate_timing)(struct timing_generator *tg,
152 void (*program_timing)(struct timing_generator *tg,
172 bool (*enable_crtc)(struct timing_generator *tg);
173 bool (*disable_crtc)(struct timing_generator *tg);
174 bool (*is_counter_moving)(struct timing_generator *tg);
175 void (*get_position)(struct timing_generator *tg,
178 uint32_t (*get_frame_count)(struct timing_generator *tg);
180 struct timing_generator *tg,
188 bool (*is_matching_timing)(struct timing_generator *tg,
190 void (*set_early_control)(struct timing_generator *tg,
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/drivers/gpu/drm/amd/display/dc/dce120/
Ddce120_timing_generator.c86 struct timing_generator *tg) in dce120_timing_generator_is_in_vertical_blank() argument
89 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_is_in_vertical_blank()
91 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
102 struct timing_generator *tg, in dce120_timing_generator_validate_timing() argument
111 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_validate_timing()
114 tg, in dce120_timing_generator_validate_timing()
128 bool dce120_tg_validate_timing(struct timing_generator *tg, in dce120_tg_validate_timing() argument
131 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
136 bool dce120_timing_generator_enable_crtc(struct timing_generator *tg) in dce120_timing_generator_enable_crtc() argument
139 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_enable_crtc()
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/drivers/gpu/drm/amd/display/dc/dce60/
Ddce60_timing_generator.c87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) in program_pix_dur() argument
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
108 static void program_timing(struct timing_generator *tg, in program_timing() argument
118 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
120 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing()
124 struct timing_generator *tg, in dce60_timing_generator_enable_advanced_request() argument
128 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce60_timing_generator_enable_advanced_request()
130 uint32_t value = dm_read_reg(tg->ctx, addr); in dce60_timing_generator_enable_advanced_request()
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Ddce60_hw_sequencer.c128 params.inst = pipe_ctx->stream_res.tg->inst; in dce60_enable_fbc()
192 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); in dce60_program_surface_visibility()
200 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in dce60_get_surface_visual_confirm_color()
251 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in dce60_program_scaler()
260 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in dce60_program_scaler()
261 pipe_ctx->stream_res.tg, in dce60_program_scaler()
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_hw_sequencer.c91 struct timing_generator *tg; in dcn10_lock_all_pipes() local
96 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
104 !tg->funcs->is_tg_enabled(tg)) in dcn10_lock_all_pipes()
343 struct timing_generator *tg = pool->timing_generators[i]; in dcn10_log_hw_state() local
346 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_log_hw_state()
358 s.blank_enabled = tg->funcs->is_blanked(tg); in dcn10_log_hw_state()
365 tg->inst, in dcn10_log_hw_state()
389 tg->funcs->clear_optc_underflow(tg); in dcn10_log_hw_state()
468 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dcn10_did_underflow_occur() local
470 if (tg->funcs->is_optc_underflow_occurred(tg)) { in dcn10_did_underflow_occur()
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Ddcn10_hw_sequencer_debug.c427 struct timing_generator *tg = pool->timing_generators[i]; in dcn10_get_otg_states() local
431 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_get_otg_states()
439 tg->inst, in dcn10_get_otg_states()
494 struct timing_generator *tg = pool->timing_generators[i]; in dcn10_clear_otpc_underflow() local
497 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_clear_otpc_underflow()
500 tg->funcs->clear_optc_underflow(tg); in dcn10_clear_otpc_underflow()
/drivers/gpu/drm/amd/display/dc/dce80/
Ddce80_timing_generator.c87 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) in program_pix_dur() argument
91 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
92 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
108 static void program_timing(struct timing_generator *tg, in program_timing() argument
118 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
120 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing()
124 struct timing_generator *tg, in dce80_timing_generator_enable_advanced_request() argument
128 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce80_timing_generator_enable_advanced_request()
130 uint32_t value = dm_read_reg(tg->ctx, addr); in dce80_timing_generator_enable_advanced_request()
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/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_hwseq.c162 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
163 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
164 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
165 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
168 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
169 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
275 struct timing_generator *tg) in dcn20_init_blank() argument
290 tg->funcs->get_otg_active_size(tg, in dcn20_init_blank()
295 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn20_init_blank()
676 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn20_enable_stream_timing()
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/drivers/gpu/drm/amd/display/dc/dce/
Ddce_hwseq.c56 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
57 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
60 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
71 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
82 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
83 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/drivers/gpu/drm/
Ddrm_connector.c2480 struct drm_tile_group *tg = container_of(kref, struct drm_tile_group, refcount); in drm_tile_group_free() local
2481 struct drm_device *dev = tg->dev; in drm_tile_group_free()
2484 idr_remove(&dev->mode_config.tile_idr, tg->id); in drm_tile_group_free()
2486 kfree(tg); in drm_tile_group_free()
2497 struct drm_tile_group *tg) in drm_mode_put_tile_group() argument
2499 kref_put(&tg->refcount, drm_tile_group_free); in drm_mode_put_tile_group()
2516 struct drm_tile_group *tg; in drm_mode_get_tile_group() local
2520 idr_for_each_entry(&dev->mode_config.tile_idr, tg, id) { in drm_mode_get_tile_group()
2521 if (!memcmp(tg->group_data, topology, 8)) { in drm_mode_get_tile_group()
2522 if (!kref_get_unless_zero(&tg->refcount)) in drm_mode_get_tile_group()
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/drivers/firmware/efi/libstub/
Darm64-stub.c20 u64 tg; in check_platform_features() local
26 tg = (read_cpuid(ID_AA64MMFR0_EL1) >> ID_AA64MMFR0_TGRAN_SHIFT) & 0xf; in check_platform_features()
27 if (tg < ID_AA64MMFR0_TGRAN_SUPPORTED_MIN || tg > ID_AA64MMFR0_TGRAN_SUPPORTED_MAX) { in check_platform_features()
/drivers/hwtracing/coresight/
Dcoresight-cti-platform.c317 struct cti_trig_grp *tg = NULL; in cti_plat_process_filter_sigs() local
328 tg = kzalloc(sizeof(*tg), GFP_KERNEL); in cti_plat_process_filter_sigs()
329 if (!tg) in cti_plat_process_filter_sigs()
332 err = cti_plat_read_trig_group(tg, fwnode, CTI_DT_FILTER_OUT_SIGS); in cti_plat_process_filter_sigs()
334 drvdata->config.trig_out_filter |= tg->used_mask; in cti_plat_process_filter_sigs()
336 kfree(tg); in cti_plat_process_filter_sigs()
/drivers/gpu/drm/amd/display/dc/core/
Ddc.c296 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_adjust_vmin_vmax()
352 struct timing_generator *tg; in dc_stream_configure_crc() local
381 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
384 if (tg->funcs->configure_crc) in dc_stream_configure_crc()
385 return tg->funcs->configure_crc(tg, &param); in dc_stream_configure_crc()
404 struct timing_generator *tg; in dc_stream_get_crc() local
415 tg = pipe->stream_res.tg; in dc_stream_get_crc()
417 if (tg->funcs->get_crc) in dc_stream_get_crc()
418 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb); in dc_stream_get_crc()
1098 pipe_set[j]->stream_res.tg->funcs->is_blanked(pipe_set[j]->stream_res.tg); in program_timing_sync()
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Ddc_hw_sequencer.c273 struct timing_generator *tg) in hwss_wait_for_blank_complete() argument
278 if (!tg->funcs->is_blanked) in hwss_wait_for_blank_complete()
281 if (tg->funcs->is_blanked(tg)) in hwss_wait_for_blank_complete()
Ddc_stream.c535 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter() local
537 if (res_ctx->pipe_ctx[i].stream != stream || !tg) in dc_stream_get_vblank_counter()
540 return tg->funcs->get_frame_count(tg); in dc_stream_get_vblank_counter()
594 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_scanoutpos() local
596 if (res_ctx->pipe_ctx[i].stream != stream || !tg) in dc_stream_get_scanoutpos()
599 tg->funcs->get_scanoutpos(tg, in dc_stream_get_scanoutpos()
Ddc_link_dp.c3873 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) in set_crtc_test_pattern()
3874 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
3937 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern) in set_crtc_test_pattern()
3938 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg, in set_crtc_test_pattern()
4149 if (pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable) { in dc_link_dp_set_test_pattern()
4155 inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst; in dc_link_dp_set_test_pattern()
4162 pipe_ctx->stream_res.tg->funcs->lock_doublebuffer_enable( in dc_link_dp_set_test_pattern()
4163 pipe_ctx->stream_res.tg); in dc_link_dp_set_test_pattern()
4166 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg); in dc_link_dp_set_test_pattern()
4185 pipe_ctx->stream_res.tg->funcs->unlock(pipe_ctx->stream_res.tg); in dc_link_dp_set_test_pattern()
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/drivers/video/fbdev/
Dw100fb.c236 struct w100_tg_info *tg = par->mach->tg; in w100fb_blank() local
245 if(tg && tg->suspend) in w100fb_blank()
246 tg->suspend(par); in w100fb_blank()
253 if(tg && tg->resume) in w100fb_blank()
254 tg->resume(par); in w100fb_blank()
414 struct w100_tg_info *tg = par->mach->tg; in w100fb_activate_var() local
430 if (!par->blanked && tg && tg->change) in w100fb_activate_var()
431 tg->change(par); in w100fb_activate_var()
608 struct w100_tg_info *tg = par->mach->tg; in w100fb_suspend() local
611 if(tg && tg->suspend) in w100fb_suspend()
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/drivers/media/platform/qcom/camss/
Dcamss-csid.c625 struct csid_testgen_config *tg = &csid->testgen; in csid_set_stream() local
642 if (!tg->enabled && in csid_set_stream()
646 if (tg->enabled) { in csid_set_stream()
677 val = tg->payload_mode; in csid_set_stream()
738 if (tg->enabled) { in csid_set_stream()
744 if (tg->enabled) { in csid_set_stream()
1023 struct csid_testgen_config *tg = &csid->testgen; in csid_set_test_pattern() local
1029 tg->enabled = !!value; in csid_set_test_pattern()
1033 tg->payload_mode = CSID_PAYLOAD_MODE_INCREMENTING; in csid_set_test_pattern()
1036 tg->payload_mode = CSID_PAYLOAD_MODE_ALTERNATING_55_AA; in csid_set_test_pattern()
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dce110/
Dirq_service_dce110.c214 struct timing_generator *tg = in dce110_vblank_set() local
215 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
218 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) { in dce110_vblank_set()
/drivers/gpu/drm/amd/display/dc/dcn21/
Ddcn21_hwseq.c164 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_abm_immediate_disable()
182 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_pipe()
202 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst; in dcn21_set_backlight_level()
/drivers/net/ethernet/mscc/
Docelot_vcap.c38 u32 tg; /* TG_DAT */ member
102 ocelot_target_write(ocelot, vcap->target, data->tg, VCAP_CACHE_TG_DAT); in vcap_entry2cache()
120 data->tg = ocelot_target_read(ocelot, vcap->target, VCAP_CACHE_TG_DAT); in vcap_cache2entry()
364 data.tg = (data.tg & ~data.tg_mask); in is2_entry_set()
366 data.tg |= data.tg_value; in is2_entry_set()
689 data.tg = (data.tg & ~data.tg_mask); in is1_entry_set()
691 data.tg |= data.tg_value; in is1_entry_set()
828 data.tg = (data.tg & ~data.tg_mask); in es0_entry_set()
830 data.tg |= data.tg_value; in es0_entry_set()

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