/drivers/net/ethernet/hisilicon/hns/ |
D | hns_dsaf_gmac.c | 154 u32 tx_ctrl; in hns_gmac_config_pad_and_crc() local 157 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); in hns_gmac_config_pad_and_crc() 158 dsaf_set_bit(tx_ctrl, GMAC_TX_PAD_EN_B, !!newval); in hns_gmac_config_pad_and_crc() 159 dsaf_set_bit(tx_ctrl, GMAC_TX_CRC_ADD_B, !!newval); in hns_gmac_config_pad_and_crc() 160 dsaf_write_dev(drv, GMAC_TRANSMIT_CONTROL_REG, tx_ctrl); in hns_gmac_config_pad_and_crc() 210 u32 tx_ctrl; in hns_gmac_port_mode_get() local 217 tx_ctrl = dsaf_read_dev(drv, GMAC_TRANSMIT_CONTROL_REG); in hns_gmac_port_mode_get() 228 port_mode->pad_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_PAD_EN_B); in hns_gmac_port_mode_get() 229 port_mode->crc_add = dsaf_get_bit(tx_ctrl, GMAC_TX_CRC_ADD_B); in hns_gmac_port_mode_get() 230 port_mode->an_enable = dsaf_get_bit(tx_ctrl, GMAC_TX_AN_EN_B); in hns_gmac_port_mode_get()
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D | hns_dsaf_xgmac.c | 43 {"xgmac_tx_mac_ctrol_frame", MAC_STATS_FIELD_OFF(tx_ctrl)}, 356 hw_stats->tx_ctrl = hns_mac_reg_read64(drv, XGMAC_TX_MACCTRLPKTS); in hns_xgmac_update_stats()
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D | hns_dsaf_mac.h | 296 u64 tx_ctrl; /* only for xgmac */ member
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/drivers/net/ethernet/seeq/ |
D | sgiseeq.c | 139 hregs->rx_ctrl = hregs->tx_ctrl = 0; in reset_hpc3_and_seeq() 284 hregs->tx_cbptr, hregs->tx_ndptr, hregs->tx_ctrl); in sgiseeq_dump_rings() 454 hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; in kick_tx() 463 unsigned long status = hregs->tx_ctrl; in sgiseeq_tx() 489 hregs->tx_ctrl = HPC3_ETXCTRL_ACTIVE; in sgiseeq_tx() 646 if (!(hregs->tx_ctrl & HPC3_ETXCTRL_ACTIVE)) in sgiseeq_start_xmit()
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/drivers/net/hippi/ |
D | rrunner.c | 604 rrpriv->info->tx_ctrl.entry_size = sizeof(struct tx_desc); in rr_init1() 605 rrpriv->info->tx_ctrl.entries = TX_RING_ENTRIES; in rr_init1() 606 rrpriv->info->tx_ctrl.mode = 0; in rr_init1() 607 rrpriv->info->tx_ctrl.pi = 0; in rr_init1() 608 set_rraddr(&rrpriv->info->tx_ctrl.rngptr, rrpriv->tx_ring_dma); in rr_init1() 1091 (((rrpriv->info->tx_ctrl.pi + 1) % TX_RING_ENTRIES) in rr_interrupt() 1279 rrpriv->info->tx_ctrl.pi); in rr_dump() 1369 rrpriv->info->tx_ctrl.entries = 0; in rr_close() 1437 txctrl = &rrpriv->info->tx_ctrl; in rr_start_xmit()
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D | rrunner.h | 788 struct ring_ctrl tx_ctrl; member
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/drivers/net/ethernet/socionext/ |
D | netsec.c | 777 const struct netsec_tx_pkt_ctrl *tx_ctrl, in netsec_set_tx_de() argument 791 (tx_ctrl->cksum_offload_flag << NETSEC_TX_SHIFT_CO) | in netsec_set_tx_de() 792 (tx_ctrl->tcp_seg_offload_flag << NETSEC_TX_SHIFT_SO) | in netsec_set_tx_de() 799 de->buf_len_info = (tx_ctrl->tcp_seg_len << 16) | desc->len; in netsec_set_tx_de() 820 struct netsec_tx_pkt_ctrl tx_ctrl = {}; in netsec_xdp_queue_one() local 863 netsec_set_tx_de(priv, tx_ring, &tx_ctrl, &tx_desc, xdpf); in netsec_xdp_queue_one() 1133 struct netsec_tx_pkt_ctrl tx_ctrl = {}; in netsec_netdev_start_xmit() local 1148 tx_ctrl.cksum_offload_flag = true; in netsec_netdev_start_xmit() 1163 tx_ctrl.tcp_seg_offload_flag = true; in netsec_netdev_start_xmit() 1164 tx_ctrl.tcp_seg_len = tso_seg_len; in netsec_netdev_start_xmit() [all …]
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/drivers/net/ethernet/nvidia/ |
D | forcedeth.c | 1578 u32 tx_ctrl = readl(base + NvRegTransmitterControl); in nv_start_tx() local 1580 tx_ctrl |= NVREG_XMITCTL_START; in nv_start_tx() 1582 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; in nv_start_tx() 1583 writel(tx_ctrl, base + NvRegTransmitterControl); in nv_start_tx() 1591 u32 tx_ctrl = readl(base + NvRegTransmitterControl); in nv_stop_tx() local 1594 tx_ctrl &= ~NVREG_XMITCTL_START; in nv_stop_tx() 1596 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; in nv_stop_tx() 1597 writel(tx_ctrl, base + NvRegTransmitterControl); in nv_stop_tx() 5381 u32 tx_ctrl, mgmt_sema; in nv_mgmt_acquire_sema() local 5394 tx_ctrl = readl(base + NvRegTransmitterControl); in nv_mgmt_acquire_sema() [all …]
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/drivers/net/ethernet/qualcomm/emac/ |
D | emac.h | 246 u64 tx_ctrl; /* control packets other than pause frame */ member
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/drivers/net/ethernet/atheros/atl1e/ |
D | atl1e.h | 279 …unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding P… member
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/drivers/net/ethernet/atheros/alx/ |
D | hw.h | 425 u64 tx_ctrl; /* TX control frames, excluding pause frames */ member
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D | hw.c | 1102 hw->stats.tx_ctrl += alx_read_mem32(hw, ALX_MIB_TX_CTRL); in alx_update_hw_stats()
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/drivers/net/ethernet/atheros/atl1c/ |
D | atl1c.h | 332 …unsigned long tx_ctrl; /* The number of packets transmitted is a control frame, excluding Pause f… member
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/drivers/net/ethernet/atheros/atlx/ |
D | atl1.h | 342 u32 tx_ctrl; /* TX control frames, excluding pause frames */ member
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/drivers/net/ethernet/alteon/ |
D | acenic.h | 580 struct ring_ctrl tx_ctrl; member
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D | acenic.c | 1288 set_aceaddr(&info->tx_ctrl.rngptr, TX_RING_BASE); in ace_init() 1293 set_aceaddr(&info->tx_ctrl.rngptr, ap->tx_ring_dma); in ace_init() 1296 info->tx_ctrl.max_len = ACE_TX_RING_ENTRIES(ap); in ace_init() 1307 info->tx_ctrl.flags = tmp; in ace_init()
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/drivers/net/wireless/ti/wlcore/ |
D | acx.h | 515 __le32 tx_ctrl; member
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