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Searched refs:uc_pll_post_div (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
Dppatomctrl.h80 uint8_t uc_pll_post_div; /* Output Parameter: PLL post divider */ member
90 uint8_t uc_pll_post_div; /*Output Parameter: PLL post divider */ member
Dppatomctrl.c399 dividers->uc_pll_post_div = in atomctrl_get_engine_pll_dividers_vi()
469 dividers->uc_pll_post_div = in atomctrl_get_dfs_pll_dividers_vi()
/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dfiji_smumgr.c889 SPLL_PDIV_A, dividers.uc_pll_post_div); in fiji_calculate_sclk_params()
903 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in fiji_calculate_sclk_params()
Diceland_smumgr.c828 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in iceland_calculate_sclk_params()
842 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in iceland_calculate_sclk_params()
Dtonga_smumgr.c571 CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div); in tonga_calculate_sclk_params()
585 uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div; in tonga_calculate_sclk_params()
Dci_smumgr.c329 SPLL_PDIV_A, dividers.uc_pll_post_div); in ci_calculate_sclk_params()
342 uint32_t vco_freq = clock * dividers.uc_pll_post_div; in ci_calculate_sclk_params()