| /drivers/staging/octeon/ |
| D | octeon-stubs.h | 46 uint64_t u64;
48 uint64_t bufs:8;
49 uint64_t ip_offset:8;
50 uint64_t vlan_valid:1;
51 uint64_t vlan_stacked:1;
52 uint64_t unassigned:1;
53 uint64_t vlan_cfi:1;
54 uint64_t vlan_id:12;
55 uint64_t pr:4;
56 uint64_t unassigned2:8;
[all …]
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| /drivers/spi/ |
| D | spi-cavium.h | 42 uint64_t u64;
45 uint64_t reserved_29_63:35;
46 uint64_t clkdiv:13;
47 uint64_t csena3:1;
48 uint64_t csena2:1;
49 uint64_t csena1:1;
50 uint64_t csena0:1;
51 uint64_t cslate:1;
52 uint64_t tritx:1;
53 uint64_t idleclks:2;
[all …]
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| /drivers/dma/ioat/ |
| D | hw.h | 92 uint64_t src_addr;
93 uint64_t dst_addr;
94 uint64_t next;
95 uint64_t rsv1;
96 uint64_t rsv2;
99 uint64_t user1;
100 uint64_t tx_cnt;
102 uint64_t user2;
125 uint64_t src_addr;
126 uint64_t dst_addr;
[all …]
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| /drivers/gpu/drm/amd/amdgpu/ |
| D | amdgpu_mes.h | 49 uint64_t default_process_quantum;
50 uint64_t default_gang_quantum;
58 uint64_t ucode_fw_gpu_addr;
61 uint64_t uc_start_addr;
65 uint64_t data_fw_gpu_addr;
68 uint64_t data_start_addr;
72 uint64_t eop_gpu_addr;
83 uint64_t sch_ctx_gpu_addr;
84 uint64_t *sch_ctx_ptr;
86 uint64_t query_status_fence_gpu_addr;
[all …]
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| D | mes_api_def.h | 93 uint64_t api_completion_fence_addr;
94 uint64_t api_completion_fence_value;
137 uint64_t number_of_entries;
138 uint64_t reserved[2];
142 uint64_t gpu_time_stamp;
147 uint64_t reserved_operation_data[2];
167 uint64_t g_sch_ctx_gpu_mc_ptr;
168 uint64_t query_status_fence_gpu_mc_ptr;
186 uint64_t page_table_base_addr;
187 uint64_t process_va_start;
[all …]
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| D | amdgpu_vm.h | 80 #define AMDGPU_PDE_BFS(a) ((uint64_t)a << 59)
84 #define AMDGPU_PTE_MTYPE_VG10(a) ((uint64_t)(a) << 57)
98 #define AMDGPU_PTE_MTYPE_NV10(a) ((uint64_t)(a) << 48)
168 uint64_t pe, uint64_t src,
172 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
173 uint64_t value, unsigned count,
177 uint64_t pe,
178 uint64_t addr, unsigned count,
179 uint32_t incr, uint64_t flags);
241 struct amdgpu_bo *bo, uint64_t pe, uint64_t addr,
[all …]
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| D | amdgpu_gmc.h | 69 uint64_t timestamp;
70 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER;
71 uint64_t key:52;
118 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid,
119 uint64_t pd_addr);
126 uint64_t (*map_mtype)(struct amdgpu_device *adev, uint32_t flags);
133 uint64_t *flags);
232 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER;
234 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER;
276 static inline uint64_t amdgpu_gmc_sign_extend(uint64_t addr) in amdgpu_gmc_sign_extend()
[all …]
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| D | amdgpu_amdkfd.h | 37 extern uint64_t amdgpu_amdkfd_total_mem_size;
46 uint64_t va;
47 uint64_t pte_flags;
59 uint64_t va;
82 uint64_t vram_used;
132 uint32_t vmid, uint64_t gpu_addr,
184 void **mem_obj, uint64_t *gpu_addr,
195 uint64_t amdgpu_amdkfd_get_gpu_clock_counter(struct kgd_dev *kgd);
201 uint64_t *bo_size, void *metadata_buffer,
204 uint64_t amdgpu_amdkfd_get_vram_usage(struct kgd_dev *kgd);
[all …]
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| D | amdgpu_ttm.h | 77 uint64_t stolen_vga_size;
79 uint64_t stolen_extended_size;
101 int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
107 uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man);
120 uint64_t amdgpu_vram_mgr_usage(struct ttm_resource_manager *man);
121 uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_resource_manager *man);
129 int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
130 uint64_t dst_offset, uint32_t byte_count,
137 uint64_t size, bool tmz,
148 uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
[all …]
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| D | amdgpu_gmc.c | 45 uint64_t *addr, uint64_t *flags) in amdgpu_gmc_get_pde_for_bo()
70 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo) in amdgpu_gmc_pd_addr()
73 uint64_t pd_addr; in amdgpu_gmc_pd_addr()
77 uint64_t flags = AMDGPU_PTE_VALID; in amdgpu_gmc_pd_addr()
99 uint32_t gpu_page_idx, uint64_t addr, in amdgpu_gmc_set_pte_pde()
100 uint64_t flags) in amdgpu_gmc_set_pte_pde()
103 uint64_t value; in amdgpu_gmc_set_pte_pde()
122 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo) in amdgpu_gmc_agp_addr()
150 uint64_t limit = (uint64_t)amdgpu_vram_limit << 20; in amdgpu_gmc_vram_location()
179 const uint64_t four_gb = 0x100000000ULL; in amdgpu_gmc_gart_location()
[all …]
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| D | amdgpu_psp.h | 73 uint64_t ring_mem_mc_addr;
112 uint64_t node_id;
132 uint64_t xgmi_shared_mc_addr;
142 uint64_t ras_shared_mc_addr;
151 uint64_t hdcp_shared_mc_addr;
160 uint64_t dtm_shared_mc_addr;
169 uint64_t rap_shared_mc_addr;
228 uint64_t fw_pri_mc_addr;
248 uint64_t tmr_mc_addr;
259 uint64_t fence_buf_mc_addr;
[all …]
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| /drivers/scsi/qla4xxx/ |
| D | ql4_fw.h | 1170 uint64_t reserved2; /* 18-1F */
1171 uint64_t reserved3; /* 20-27 */
1172 uint64_t reserved4; /* 28-2F */
1173 uint64_t reserved5; /* 30-37 */
1174 uint64_t reserved6; /* 38-3F */
1292 uint64_t mac_tx_frames; /* 0000–0007 */
1293 uint64_t mac_tx_bytes; /* 0008–000F */
1294 uint64_t mac_tx_multicast_frames; /* 0010–0017 */
1295 uint64_t mac_tx_broadcast_frames; /* 0018–001F */
1296 uint64_t mac_tx_pause_frames; /* 0020–0027 */
[all …]
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | bw_fixed.c | 41 static uint64_t abs_i64(int64_t arg) in abs_i64()
44 return (uint64_t)(arg); in abs_i64()
46 return (uint64_t)(-arg); in abs_i64()
62 uint64_t arg1_value; in bw_frc_to_fixed()
63 uint64_t arg2_value; in bw_frc_to_fixed()
64 uint64_t remainder; in bw_frc_to_fixed()
67 uint64_t res_value; in bw_frc_to_fixed()
97 uint64_t summand = (remainder << 1) >= arg2_value; in bw_frc_to_fixed()
149 uint64_t arg1_value = abs_i64(arg1.value); in bw_mul()
150 uint64_t arg2_value = abs_i64(arg2.value); in bw_mul()
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dchubbub.h | 75 uint64_t fb_top;
76 uint64_t fb_offset;
77 uint64_t fb_base;
78 uint64_t agp_top;
79 uint64_t agp_bot;
80 uint64_t agp_base;
84 uint64_t page_table_start_addr;
85 uint64_t page_table_end_addr;
86 uint64_t page_table_base_addr;
89 uint64_t page_table_default_page_addr;
[all …]
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| /drivers/gpu/drm/amd/amdkfd/ |
| D | kfd_priv.h | 74 #define KFD_MMAP_GPU_ID(gpu_id) ((((uint64_t)gpu_id) << KFD_MMAP_GPU_ID_SHIFT)\
211 uint64_t gpu_addr;
253 uint64_t gtt_start_gpu_addr;
293 uint64_t hive_id;
296 uint64_t unique_id;
441 uint64_t queue_address;
442 uint64_t queue_size;
460 uint64_t eop_ring_buffer_address;
462 uint64_t ctx_save_restore_area_address;
465 uint64_t tba_addr;
[all …]
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| D | kfd_kernel_queue.h | 58 uint64_t pending_wptr64;
64 uint64_t rptr_gpu_addr;
67 uint64_t *wptr64_kernel;
70 uint64_t wptr_gpu_addr;
72 uint64_t pq_gpu_addr;
75 uint64_t eop_gpu_addr;
79 uint64_t fence_gpu_addr;
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| D | kfd_device_queue_manager.h | 122 uint64_t alternate_aperture_size);
126 uint64_t tba_addr,
127 uint64_t tma_addr);
152 uint64_t alternate_aperture_size);
189 uint64_t sdma_bitmap;
190 uint64_t xgmi_sdma_bitmap;
193 uint64_t pipelines_addr;
194 uint64_t fence_gpu_addr;
195 uint64_t *fence_addr;
254 static inline int read_sdma_queue_counter(uint64_t __user *q_rptr, uint64_t *val) in read_sdma_queue_counter()
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| /drivers/md/persistent-data/ |
| D | dm-btree.h | 110 uint64_t *keys, void *value_le);
117 uint64_t *keys, uint64_t *rkey, void *value_le);
123 uint64_t *keys, void *value, dm_block_t *new_root)
132 uint64_t *keys, void *value, dm_block_t *new_root,
142 uint64_t *keys, dm_block_t *new_root);
151 uint64_t *keys, uint64_t end_key,
160 uint64_t *result_keys);
168 uint64_t *result_keys);
176 int (*fn)(void *context, uint64_t *keys, void *leaf),
213 int dm_btree_cursor_get_value(struct dm_btree_cursor *c, uint64_t *key, void *value_le);
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| /drivers/scsi/lpfc/ |
| D | lpfc_sli.h | 67 uint64_t isr_timestamp;
192 uint64_t iocb_event; /* IOCB event counters */
193 uint64_t iocb_cmd; /* IOCB cmd issued */
194 uint64_t iocb_rsp; /* IOCB rsp received */
195 uint64_t iocb_cmd_delay; /* IOCB cmd ring delay */
196 uint64_t iocb_cmd_full; /* IOCB cmd ring full */
197 uint64_t iocb_cmd_empty; /* IOCB cmd ring is now empty */
198 uint64_t iocb_rsp_full; /* IOCB rsp ring full */
293 uint64_t mbox_stat_err; /* Mbox cmds completed status error */
294 uint64_t mbox_cmd; /* Mailbox commands issued */
[all …]
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| D | lpfc.h | 877 uint64_t cfg_soft_wwnn;
878 uint64_t cfg_soft_wwpn;
1007 uint64_t bg_guard_err_cnt;
1008 uint64_t bg_apptag_err_cnt;
1009 uint64_t bg_reftag_err_cnt;
1212 uint64_t ktime_data_samples;
1213 uint64_t ktime_status_samples;
1214 uint64_t ktime_last_cmd;
1215 uint64_t ktime_seg1_total;
1216 uint64_t ktime_seg1_min;
[all …]
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| /drivers/gpu/drm/selftests/ |
| D | test-drm_format.c | 125 (uint64_t)UINT_MAX); in igt_check_drm_format_min_pitch()
127 (uint64_t)(UINT_MAX - 1)); in igt_check_drm_format_min_pitch()
144 (uint64_t)UINT_MAX * 2); in igt_check_drm_format_min_pitch()
146 (uint64_t)(UINT_MAX - 1) * 2); in igt_check_drm_format_min_pitch()
163 (uint64_t)UINT_MAX * 3); in igt_check_drm_format_min_pitch()
165 (uint64_t)(UINT_MAX - 1) * 3); in igt_check_drm_format_min_pitch()
182 (uint64_t)UINT_MAX * 4); in igt_check_drm_format_min_pitch()
184 (uint64_t)(UINT_MAX - 1) * 4); in igt_check_drm_format_min_pitch()
209 (uint64_t)UINT_MAX); in igt_check_drm_format_min_pitch()
211 (uint64_t)UINT_MAX + 1); in igt_check_drm_format_min_pitch()
[all …]
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| /drivers/gpu/drm/ttm/ |
| D | ttm_memory.c | 51 uint64_t zone_mem;
52 uint64_t emer_mem;
53 uint64_t max_mem;
54 uint64_t swap_limit;
55 uint64_t used_mem;
95 uint64_t val = 0; in ttm_mem_zone_show()
125 uint64_t val64; in ttm_mem_zone_store()
185 uint64_t val = 0; in ttm_mem_global_show()
202 uint64_t val64; in ttm_mem_global_store()
238 bool from_wq, uint64_t extra) in ttm_zones_above_swap_target()
[all …]
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| /drivers/gpu/drm/radeon/ |
| D | radeon_asic.h | 70 uint64_t r100_pci_gart_get_page_entry(uint64_t addr, uint32_t flags);
72 uint64_t entry);
86 uint64_t src_offset,
87 uint64_t dst_offset,
157 uint64_t src_offset,
158 uint64_t dst_offset,
176 extern uint64_t rv370_pcie_gart_get_page_entry(uint64_t addr, uint32_t flags);
178 uint64_t entry);
213 uint64_t rs400_gart_get_page_entry(uint64_t addr, uint32_t flags);
215 uint64_t entry);
[all …]
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| /drivers/fsi/ |
| D | fsi-scom.c | 76 static int __put_scom(struct scom_device *scom_dev, uint64_t value, in __put_scom()
108 static int __get_scom(struct scom_device *scom_dev, uint64_t *value, in __get_scom()
134 *value |= (uint64_t)be32_to_cpu(data) << 32; in __get_scom()
145 static int put_indirect_scom_form0(struct scom_device *scom, uint64_t value, in put_indirect_scom_form0()
146 uint64_t addr, uint32_t *status) in put_indirect_scom_form0()
148 uint64_t ind_data, ind_addr; in put_indirect_scom_form0()
175 static int put_indirect_scom_form1(struct scom_device *scom, uint64_t value, in put_indirect_scom_form1()
176 uint64_t addr, uint32_t *status) in put_indirect_scom_form1()
178 uint64_t ind_data, ind_addr; in put_indirect_scom_form1()
188 static int get_indirect_scom_form0(struct scom_device *scom, uint64_t *value, in get_indirect_scom_form0()
[all …]
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| /drivers/gpu/drm/msm/adreno/ |
| D | a5xx_gpu.h | 19 uint64_t pm4_iova;
22 uint64_t pfp_iova;
25 uint64_t gpmu_iova;
36 uint64_t preempt_iova[MSM_GPU_MAX_RINGS];
42 uint64_t shadow_iova;
113 uint64_t rptr_addr;
114 uint64_t rbase;
115 uint64_t counter;
|