1 /* 2 * Copyright 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dc_features.h" 27 #include "display_mode_enums.h" 28 29 #ifndef __DISPLAY_MODE_STRUCTS_H__ 30 #define __DISPLAY_MODE_STRUCTS_H__ 31 32 typedef struct _vcs_dpi_voltage_scaling_st voltage_scaling_st; 33 typedef struct _vcs_dpi_soc_bounding_box_st soc_bounding_box_st; 34 typedef struct _vcs_dpi_ip_params_st ip_params_st; 35 typedef struct _vcs_dpi_display_pipe_source_params_st display_pipe_source_params_st; 36 typedef struct _vcs_dpi_display_output_params_st display_output_params_st; 37 typedef struct _vcs_dpi_scaler_ratio_depth_st scaler_ratio_depth_st; 38 typedef struct _vcs_dpi_scaler_taps_st scaler_taps_st; 39 typedef struct _vcs_dpi_display_pipe_dest_params_st display_pipe_dest_params_st; 40 typedef struct _vcs_dpi_display_pipe_params_st display_pipe_params_st; 41 typedef struct _vcs_dpi_display_clocks_and_cfg_st display_clocks_and_cfg_st; 42 typedef struct _vcs_dpi_display_e2e_pipe_params_st display_e2e_pipe_params_st; 43 typedef struct _vcs_dpi_display_data_rq_misc_params_st display_data_rq_misc_params_st; 44 typedef struct _vcs_dpi_display_data_rq_sizing_params_st display_data_rq_sizing_params_st; 45 typedef struct _vcs_dpi_display_data_rq_dlg_params_st display_data_rq_dlg_params_st; 46 typedef struct _vcs_dpi_display_rq_dlg_params_st display_rq_dlg_params_st; 47 typedef struct _vcs_dpi_display_rq_sizing_params_st display_rq_sizing_params_st; 48 typedef struct _vcs_dpi_display_rq_misc_params_st display_rq_misc_params_st; 49 typedef struct _vcs_dpi_display_rq_params_st display_rq_params_st; 50 typedef struct _vcs_dpi_display_dlg_regs_st display_dlg_regs_st; 51 typedef struct _vcs_dpi_display_ttu_regs_st display_ttu_regs_st; 52 typedef struct _vcs_dpi_display_data_rq_regs_st display_data_rq_regs_st; 53 typedef struct _vcs_dpi_display_rq_regs_st display_rq_regs_st; 54 typedef struct _vcs_dpi_display_dlg_sys_params_st display_dlg_sys_params_st; 55 typedef struct _vcs_dpi_display_arb_params_st display_arb_params_st; 56 57 struct _vcs_dpi_voltage_scaling_st { 58 int state; 59 double dscclk_mhz; 60 double dcfclk_mhz; 61 double socclk_mhz; 62 double phyclk_d18_mhz; 63 double dram_speed_mts; 64 double fabricclk_mhz; 65 double dispclk_mhz; 66 double dram_bw_per_chan_gbps; 67 double phyclk_mhz; 68 double dppclk_mhz; 69 double dtbclk_mhz; 70 }; 71 72 struct _vcs_dpi_soc_bounding_box_st { 73 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 74 unsigned int num_states; 75 double sr_exit_time_us; 76 double sr_enter_plus_exit_time_us; 77 double urgent_latency_us; 78 double urgent_latency_pixel_data_only_us; 79 double urgent_latency_pixel_mixed_with_vm_data_us; 80 double urgent_latency_vm_data_only_us; 81 double writeback_latency_us; 82 double ideal_dram_bw_after_urgent_percent; 83 double pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly 84 double pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm; 85 double pct_ideal_dram_sdp_bw_after_urgent_vm_only; 86 double pct_ideal_sdp_bw_after_urgent; 87 double max_avg_sdp_bw_use_normal_percent; 88 double max_avg_dram_bw_use_normal_percent; 89 unsigned int max_request_size_bytes; 90 double downspread_percent; 91 double dram_page_open_time_ns; 92 double dram_rw_turnaround_time_ns; 93 double dram_return_buffer_per_channel_bytes; 94 double dram_channel_width_bytes; 95 double fabric_datapath_to_dcn_data_return_bytes; 96 double dcn_downspread_percent; 97 double dispclk_dppclk_vco_speed_mhz; 98 double dfs_vco_period_ps; 99 unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes; 100 unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes; 101 unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes; 102 unsigned int round_trip_ping_latency_dcfclk_cycles; 103 unsigned int urgent_out_of_order_return_per_channel_bytes; 104 unsigned int channel_interleave_bytes; 105 unsigned int num_banks; 106 unsigned int num_chans; 107 unsigned int vmm_page_size_bytes; 108 unsigned int hostvm_min_page_size_bytes; 109 unsigned int gpuvm_min_page_size_bytes; 110 double dram_clock_change_latency_us; 111 double dummy_pstate_latency_us; 112 double writeback_dram_clock_change_latency_us; 113 unsigned int return_bus_width_bytes; 114 unsigned int voltage_override; 115 double xfc_bus_transport_time_us; 116 double xfc_xbuf_latency_tolerance_us; 117 int use_urgent_burst_bw; 118 double min_dcfclk; 119 bool do_urgent_latency_adjustment; 120 double urgent_latency_adjustment_fabric_clock_component_us; 121 double urgent_latency_adjustment_fabric_clock_reference_mhz; 122 bool disable_dram_clock_change_vactive_support; 123 bool allow_dram_clock_one_display_vactive; 124 enum self_refresh_affinity allow_dram_self_refresh_or_dram_clock_change_in_vblank; 125 }; 126 127 struct _vcs_dpi_ip_params_st { 128 bool use_min_dcfclk; 129 #ifdef CONFIG_DRM_AMD_DC_DCN3_0 130 bool clamp_min_dcfclk; 131 #endif 132 bool gpuvm_enable; 133 bool hostvm_enable; 134 bool dsc422_native_support; 135 unsigned int gpuvm_max_page_table_levels; 136 unsigned int hostvm_max_page_table_levels; 137 unsigned int hostvm_cached_page_table_levels; 138 unsigned int pte_group_size_bytes; 139 unsigned int max_inter_dcn_tile_repeaters; 140 unsigned int num_dsc; 141 unsigned int odm_capable; 142 unsigned int rob_buffer_size_kbytes; 143 unsigned int det_buffer_size_kbytes; 144 unsigned int dpte_buffer_size_in_pte_reqs_luma; 145 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 146 unsigned int pde_proc_buffer_size_64k_reqs; 147 unsigned int dpp_output_buffer_pixels; 148 unsigned int opp_output_buffer_lines; 149 unsigned int pixel_chunk_size_kbytes; 150 unsigned char pte_enable; 151 unsigned int pte_chunk_size_kbytes; 152 unsigned int meta_chunk_size_kbytes; 153 unsigned int min_meta_chunk_size_bytes; 154 unsigned int writeback_chunk_size_kbytes; 155 unsigned int line_buffer_size_bits; 156 unsigned int max_line_buffer_lines; 157 unsigned int writeback_luma_buffer_size_kbytes; 158 unsigned int writeback_chroma_buffer_size_kbytes; 159 unsigned int writeback_chroma_line_buffer_width_pixels; 160 161 unsigned int writeback_interface_buffer_size_kbytes; 162 unsigned int writeback_line_buffer_buffer_size; 163 164 unsigned int writeback_10bpc420_supported; 165 double writeback_max_hscl_ratio; 166 double writeback_max_vscl_ratio; 167 double writeback_min_hscl_ratio; 168 double writeback_min_vscl_ratio; 169 double maximum_dsc_bits_per_component; 170 unsigned int writeback_max_hscl_taps; 171 unsigned int writeback_max_vscl_taps; 172 unsigned int writeback_line_buffer_luma_buffer_size; 173 unsigned int writeback_line_buffer_chroma_buffer_size; 174 175 unsigned int max_page_table_levels; 176 unsigned int max_num_dpp; 177 unsigned int max_num_otg; 178 unsigned int cursor_chunk_size; 179 unsigned int cursor_buffer_size; 180 unsigned int max_num_wb; 181 unsigned int max_dchub_pscl_bw_pix_per_clk; 182 unsigned int max_pscl_lb_bw_pix_per_clk; 183 unsigned int max_lb_vscl_bw_pix_per_clk; 184 unsigned int max_vscl_hscl_bw_pix_per_clk; 185 double max_hscl_ratio; 186 double max_vscl_ratio; 187 unsigned int hscl_mults; 188 unsigned int vscl_mults; 189 unsigned int max_hscl_taps; 190 unsigned int max_vscl_taps; 191 unsigned int xfc_supported; 192 unsigned int ptoi_supported; 193 unsigned int gfx7_compat_tiling_supported; 194 195 bool odm_combine_4to1_supported; 196 bool dynamic_metadata_vm_enabled; 197 unsigned int max_num_hdmi_frl_outputs; 198 199 unsigned int xfc_fill_constant_bytes; 200 double dispclk_ramp_margin_percent; 201 double xfc_fill_bw_overhead_percent; 202 double underscan_factor; 203 unsigned int min_vblank_lines; 204 unsigned int dppclk_delay_subtotal; 205 unsigned int dispclk_delay_subtotal; 206 double dcfclk_cstate_latency; 207 unsigned int dppclk_delay_scl; 208 unsigned int dppclk_delay_scl_lb_only; 209 unsigned int dppclk_delay_cnvc_formatter; 210 unsigned int dppclk_delay_cnvc_cursor; 211 unsigned int is_line_buffer_bpp_fixed; 212 unsigned int line_buffer_fixed_bpp; 213 unsigned int dcc_supported; 214 215 unsigned int IsLineBufferBppFixed; 216 unsigned int LineBufferFixedBpp; 217 unsigned int can_vstartup_lines_exceed_vsync_plus_back_porch_lines_minus_one; 218 unsigned int bug_forcing_LC_req_same_size_fixed; 219 unsigned int number_of_cursors; 220 }; 221 222 struct _vcs_dpi_display_xfc_params_st { 223 double xfc_tslv_vready_offset_us; 224 double xfc_tslv_vupdate_width_us; 225 double xfc_tslv_vupdate_offset_us; 226 int xfc_slv_chunk_size_bytes; 227 }; 228 229 struct _vcs_dpi_display_pipe_source_params_st { 230 int source_format; 231 double dcc_fraction_of_zs_req_luma; 232 double dcc_fraction_of_zs_req_chroma; 233 unsigned char dcc; 234 unsigned int dcc_rate; 235 unsigned int dcc_rate_chroma; 236 unsigned char dcc_use_global; 237 unsigned char vm; 238 bool unbounded_req_mode; 239 bool gpuvm; // gpuvm enabled 240 bool hostvm; // hostvm enabled 241 bool gpuvm_levels_force_en; 242 unsigned int gpuvm_levels_force; 243 bool hostvm_levels_force_en; 244 unsigned int hostvm_levels_force; 245 int source_scan; 246 int sw_mode; 247 int macro_tile_size; 248 unsigned int surface_width_y; 249 unsigned int surface_height_y; 250 unsigned int surface_width_c; 251 unsigned int surface_height_c; 252 unsigned int viewport_width; 253 unsigned int viewport_height; 254 unsigned int viewport_y_y; 255 unsigned int viewport_y_c; 256 unsigned int viewport_width_c; 257 unsigned int viewport_height_c; 258 unsigned int data_pitch; 259 unsigned int data_pitch_c; 260 unsigned int meta_pitch; 261 unsigned int meta_pitch_c; 262 unsigned int cur0_src_width; 263 int cur0_bpp; 264 unsigned int cur1_src_width; 265 int cur1_bpp; 266 int num_cursors; 267 unsigned char is_hsplit; 268 unsigned char dynamic_metadata_enable; 269 unsigned int dynamic_metadata_lines_before_active; 270 unsigned int dynamic_metadata_xmit_bytes; 271 unsigned int hsplit_grp; 272 unsigned char xfc_enable; 273 unsigned char xfc_slave; 274 unsigned char immediate_flip; 275 struct _vcs_dpi_display_xfc_params_st xfc_params; 276 //for vstartuplines calculation freesync 277 unsigned char v_total_min; 278 unsigned char v_total_max; 279 }; 280 struct writeback_st { 281 int wb_src_height; 282 int wb_src_width; 283 int wb_dst_width; 284 int wb_dst_height; 285 int wb_pixel_format; 286 int wb_htaps_luma; 287 int wb_vtaps_luma; 288 int wb_htaps_chroma; 289 int wb_vtaps_chroma; 290 double wb_hratio; 291 double wb_vratio; 292 }; 293 294 struct _vcs_dpi_display_output_params_st { 295 int dp_lanes; 296 double output_bpp; 297 int dsc_enable; 298 int wb_enable; 299 int num_active_wb; 300 int output_bpc; 301 int output_type; 302 int output_format; 303 int dsc_slices; 304 int max_audio_sample_rate; 305 struct writeback_st wb; 306 }; 307 308 struct _vcs_dpi_scaler_ratio_depth_st { 309 double hscl_ratio; 310 double vscl_ratio; 311 double hscl_ratio_c; 312 double vscl_ratio_c; 313 double vinit; 314 double vinit_c; 315 double vinit_bot; 316 double vinit_bot_c; 317 int lb_depth; 318 int scl_enable; 319 }; 320 321 struct _vcs_dpi_scaler_taps_st { 322 unsigned int htaps; 323 unsigned int vtaps; 324 unsigned int htaps_c; 325 unsigned int vtaps_c; 326 }; 327 328 struct _vcs_dpi_display_pipe_dest_params_st { 329 unsigned int recout_width; 330 unsigned int recout_height; 331 unsigned int full_recout_width; 332 unsigned int full_recout_height; 333 unsigned int hblank_start; 334 unsigned int hblank_end; 335 unsigned int vblank_start; 336 unsigned int vblank_end; 337 unsigned int htotal; 338 unsigned int vtotal; 339 unsigned int refresh_rate; 340 unsigned int vfront_porch; 341 unsigned int vactive; 342 unsigned int hactive; 343 unsigned int vstartup_start; 344 unsigned int vupdate_offset; 345 unsigned int vupdate_width; 346 unsigned int vready_offset; 347 unsigned char interlaced; 348 double pixel_rate_mhz; 349 unsigned char synchronized_vblank_all_planes; 350 unsigned char synchronize_timing_if_single_refresh_rate; 351 unsigned char otg_inst; 352 unsigned int odm_combine; 353 unsigned char use_maximum_vstartup; 354 unsigned int vtotal_max; 355 unsigned int vtotal_min; 356 }; 357 358 struct _vcs_dpi_display_pipe_params_st { 359 display_pipe_source_params_st src; 360 display_pipe_dest_params_st dest; 361 scaler_ratio_depth_st scale_ratio_depth; 362 scaler_taps_st scale_taps; 363 }; 364 365 struct _vcs_dpi_display_clocks_and_cfg_st { 366 int voltage; 367 double dppclk_mhz; 368 double refclk_mhz; 369 double dispclk_mhz; 370 double dcfclk_mhz; 371 double socclk_mhz; 372 }; 373 374 struct _vcs_dpi_display_e2e_pipe_params_st { 375 display_pipe_params_st pipe; 376 display_output_params_st dout; 377 display_clocks_and_cfg_st clks_cfg; 378 }; 379 380 struct _vcs_dpi_display_data_rq_misc_params_st { 381 unsigned int full_swath_bytes; 382 unsigned int stored_swath_bytes; 383 unsigned int blk256_height; 384 unsigned int blk256_width; 385 unsigned int req_height; 386 unsigned int req_width; 387 }; 388 389 struct _vcs_dpi_display_data_rq_sizing_params_st { 390 unsigned int chunk_bytes; 391 unsigned int min_chunk_bytes; 392 unsigned int meta_chunk_bytes; 393 unsigned int min_meta_chunk_bytes; 394 unsigned int mpte_group_bytes; 395 unsigned int dpte_group_bytes; 396 }; 397 398 struct _vcs_dpi_display_data_rq_dlg_params_st { 399 unsigned int swath_width_ub; 400 unsigned int swath_height; 401 unsigned int req_per_swath_ub; 402 unsigned int meta_pte_bytes_per_frame_ub; 403 unsigned int dpte_req_per_row_ub; 404 unsigned int dpte_groups_per_row_ub; 405 unsigned int dpte_row_height; 406 unsigned int dpte_bytes_per_row_ub; 407 unsigned int meta_chunks_per_row_ub; 408 unsigned int meta_req_per_row_ub; 409 unsigned int meta_row_height; 410 unsigned int meta_bytes_per_row_ub; 411 }; 412 413 struct _vcs_dpi_display_rq_dlg_params_st { 414 display_data_rq_dlg_params_st rq_l; 415 display_data_rq_dlg_params_st rq_c; 416 }; 417 418 struct _vcs_dpi_display_rq_sizing_params_st { 419 display_data_rq_sizing_params_st rq_l; 420 display_data_rq_sizing_params_st rq_c; 421 }; 422 423 struct _vcs_dpi_display_rq_misc_params_st { 424 display_data_rq_misc_params_st rq_l; 425 display_data_rq_misc_params_st rq_c; 426 }; 427 428 struct _vcs_dpi_display_rq_params_st { 429 unsigned char yuv420; 430 unsigned char yuv420_10bpc; 431 unsigned char rgbe_alpha; 432 display_rq_misc_params_st misc; 433 display_rq_sizing_params_st sizing; 434 display_rq_dlg_params_st dlg; 435 }; 436 437 struct _vcs_dpi_display_dlg_regs_st { 438 unsigned int refcyc_h_blank_end; 439 unsigned int dlg_vblank_end; 440 unsigned int min_dst_y_next_start; 441 unsigned int refcyc_per_htotal; 442 unsigned int refcyc_x_after_scaler; 443 unsigned int dst_y_after_scaler; 444 unsigned int dst_y_prefetch; 445 unsigned int dst_y_per_vm_vblank; 446 unsigned int dst_y_per_row_vblank; 447 unsigned int dst_y_per_vm_flip; 448 unsigned int dst_y_per_row_flip; 449 unsigned int ref_freq_to_pix_freq; 450 unsigned int vratio_prefetch; 451 unsigned int vratio_prefetch_c; 452 unsigned int refcyc_per_pte_group_vblank_l; 453 unsigned int refcyc_per_pte_group_vblank_c; 454 unsigned int refcyc_per_meta_chunk_vblank_l; 455 unsigned int refcyc_per_meta_chunk_vblank_c; 456 unsigned int refcyc_per_pte_group_flip_l; 457 unsigned int refcyc_per_pte_group_flip_c; 458 unsigned int refcyc_per_meta_chunk_flip_l; 459 unsigned int refcyc_per_meta_chunk_flip_c; 460 unsigned int dst_y_per_pte_row_nom_l; 461 unsigned int dst_y_per_pte_row_nom_c; 462 unsigned int refcyc_per_pte_group_nom_l; 463 unsigned int refcyc_per_pte_group_nom_c; 464 unsigned int dst_y_per_meta_row_nom_l; 465 unsigned int dst_y_per_meta_row_nom_c; 466 unsigned int refcyc_per_meta_chunk_nom_l; 467 unsigned int refcyc_per_meta_chunk_nom_c; 468 unsigned int refcyc_per_line_delivery_pre_l; 469 unsigned int refcyc_per_line_delivery_pre_c; 470 unsigned int refcyc_per_line_delivery_l; 471 unsigned int refcyc_per_line_delivery_c; 472 unsigned int chunk_hdl_adjust_cur0; 473 unsigned int chunk_hdl_adjust_cur1; 474 unsigned int vready_after_vcount0; 475 unsigned int dst_y_offset_cur0; 476 unsigned int dst_y_offset_cur1; 477 unsigned int xfc_reg_transfer_delay; 478 unsigned int xfc_reg_precharge_delay; 479 unsigned int xfc_reg_remote_surface_flip_latency; 480 unsigned int xfc_reg_prefetch_margin; 481 unsigned int dst_y_delta_drq_limit; 482 unsigned int refcyc_per_vm_group_vblank; 483 unsigned int refcyc_per_vm_group_flip; 484 unsigned int refcyc_per_vm_req_vblank; 485 unsigned int refcyc_per_vm_req_flip; 486 unsigned int refcyc_per_vm_dmdata; 487 unsigned int dmdata_dl_delta; 488 }; 489 490 struct _vcs_dpi_display_ttu_regs_st { 491 unsigned int qos_level_low_wm; 492 unsigned int qos_level_high_wm; 493 unsigned int min_ttu_vblank; 494 unsigned int qos_level_flip; 495 unsigned int refcyc_per_req_delivery_l; 496 unsigned int refcyc_per_req_delivery_c; 497 unsigned int refcyc_per_req_delivery_cur0; 498 unsigned int refcyc_per_req_delivery_cur1; 499 unsigned int refcyc_per_req_delivery_pre_l; 500 unsigned int refcyc_per_req_delivery_pre_c; 501 unsigned int refcyc_per_req_delivery_pre_cur0; 502 unsigned int refcyc_per_req_delivery_pre_cur1; 503 unsigned int qos_level_fixed_l; 504 unsigned int qos_level_fixed_c; 505 unsigned int qos_level_fixed_cur0; 506 unsigned int qos_level_fixed_cur1; 507 unsigned int qos_ramp_disable_l; 508 unsigned int qos_ramp_disable_c; 509 unsigned int qos_ramp_disable_cur0; 510 unsigned int qos_ramp_disable_cur1; 511 }; 512 513 struct _vcs_dpi_display_data_rq_regs_st { 514 unsigned int chunk_size; 515 unsigned int min_chunk_size; 516 unsigned int meta_chunk_size; 517 unsigned int min_meta_chunk_size; 518 unsigned int dpte_group_size; 519 unsigned int mpte_group_size; 520 unsigned int swath_height; 521 unsigned int pte_row_height_linear; 522 }; 523 524 struct _vcs_dpi_display_rq_regs_st { 525 display_data_rq_regs_st rq_regs_l; 526 display_data_rq_regs_st rq_regs_c; 527 unsigned int drq_expansion_mode; 528 unsigned int prq_expansion_mode; 529 unsigned int mrq_expansion_mode; 530 unsigned int crq_expansion_mode; 531 unsigned int plane1_base_address; 532 }; 533 534 struct _vcs_dpi_display_dlg_sys_params_st { 535 double t_mclk_wm_us; 536 double t_urg_wm_us; 537 double t_sr_wm_us; 538 double t_extra_us; 539 double mem_trip_us; 540 double t_srx_delay_us; 541 double deepsleep_dcfclk_mhz; 542 double total_flip_bw; 543 unsigned int total_flip_bytes; 544 }; 545 546 struct _vcs_dpi_display_arb_params_st { 547 int max_req_outstanding; 548 int min_req_outstanding; 549 int sat_level_us; 550 }; 551 552 #endif /*__DISPLAY_MODE_STRUCTS_H__*/ 553