| /drivers/gpu/ipu-v3/ |
| D | ipu-cpmem.c | 474 unsigned int u_offset, unsigned int v_offset) in ipu_cpmem_set_yuv_planar_full() argument
476 WARN_ON_ONCE((u_offset & 0x7) || (v_offset & 0x7)); in ipu_cpmem_set_yuv_planar_full()
480 ipu_ch_param_write_field(ch, IPU_FIELD_VBO, v_offset / 8); in ipu_cpmem_set_yuv_planar_full()
767 int offset, u_offset, v_offset; in ipu_cpmem_set_image() local
785 v_offset = image->v_offset ? in ipu_cpmem_set_image()
786 image->v_offset : V_OFFSET(pix, image->rect.left, in ipu_cpmem_set_image()
790 u_offset, v_offset); in ipu_cpmem_set_image()
797 v_offset = image->v_offset ? in ipu_cpmem_set_image()
798 image->v_offset : U_OFFSET(pix, image->rect.left, in ipu_cpmem_set_image()
802 u_offset, v_offset); in ipu_cpmem_set_image()
[all …]
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| D | ipu-image-convert.c | 1344 tile_image.v_offset = image->tile[tile_idx[0]].v_off; in init_idmac_channel()
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| /drivers/media/pci/saa7146/ |
| D | hexium_orion.c | 180 .v_offset = 16, .v_field = 288,
185 .v_offset = 16, .v_field = 240,
190 .v_offset = 16, .v_field = 288,
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| D | hexium_gemini.c | 130 .v_offset = 28, .v_field = 288,
135 .v_offset = 28, .v_field = 240,
140 .v_offset = 28, .v_field = 288,
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| D | mxb.c | 792 .v_offset = 0x17, .v_field = 288,
797 .v_offset = 0x17, .v_field = 288,
802 .v_offset = 0x16, .v_field = 240,
807 .v_offset = 0x14, .v_field = 288,
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| /drivers/dma/ipu/ |
| D | ipu_idmac.c | 274 u32 u_offset, u32 v_offset) in ipu_ch_param_set_plane_offset() argument
278 params->pp.vbo_l = v_offset & 0x1ffff; in ipu_ch_param_set_plane_offset()
279 params->pp.vbo_h = v_offset >> 17; in ipu_ch_param_set_plane_offset()
287 u32 v_offset; in ipu_ch_param_set_size() local
392 v_offset = u_offset + u_offset / 4; in ipu_ch_param_set_size()
393 ipu_ch_param_set_plane_offset(params, u_offset, v_offset); in ipu_ch_param_set_size()
400 v_offset = stride * height; in ipu_ch_param_set_size()
401 u_offset = v_offset + v_offset / 2; in ipu_ch_param_set_size()
402 ipu_ch_param_set_plane_offset(params, u_offset, v_offset); in ipu_ch_param_set_size()
410 v_offset = u_offset + u_offset / 2; in ipu_ch_param_set_size()
[all …]
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| /drivers/media/pci/ttpci/ |
| D | av7110_v4l.c | 865 .v_offset = 0x15, .v_field = 288,
870 .v_offset = 0x10, .v_field = 244,
879 .v_offset = 0x1b, .v_field = 288,
884 .v_offset = 0x10, .v_field = 244,
893 .v_offset = 0x14, .v_field = 288,
898 .v_offset = 0x10, .v_field = 244,
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| D | budget-av.c | 1511 .v_offset = 0x17,.v_field = 288,
1516 .v_offset = 0x16,.v_field = 240,
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| /drivers/gpu/drm/radeon/ |
| D | radeon_legacy_tv.c | 430 int v_offset, h_offset; in radeon_legacy_tv_init_restarts() local
486 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(NTSC_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
488 v_offset = ((int)(v_total * h_total) * 2 * tv_dac->v_pos) / (int)(PAL_TV_LINES_PER_FRAME); in radeon_legacy_tv_init_restarts()
490 restart -= v_offset + h_offset; in radeon_legacy_tv_init_restarts()
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| /drivers/staging/media/rkisp1/ |
| D | rkisp1-resizer.c | 91 u32 v_offset; member
133 .v_offset = RKISP1_CIF_DUAL_CROP_M_V_OFFS,
175 .v_offset = RKISP1_CIF_DUAL_CROP_S_V_OFFS,
245 rkisp1_write(rkisp1, sink_crop->top, rsz->config->dual_crop.v_offset); in rkisp1_dcrop_config()
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| /drivers/gpu/drm/tegra/ |
| D | dc.c | 342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; in tegra_dc_setup_window() local
367 v_offset = window->src.y; in tegra_dc_setup_window()
375 v_offset += window->src.h - 1; in tegra_dc_setup_window()
414 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); in tegra_dc_setup_window()
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| /drivers/media/common/saa7146/ |
| D | saa7146_hlp.c | 26 hyo = vv->standard->v_offset; in calculate_hxo_and_hyo()
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