| /drivers/net/wireless/realtek/rtw88/ |
| D | fw.h | 246 #define SET_PKT_H2C_CATEGORY(h2c_pkt, value) \ argument
247 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(6, 0))
248 #define SET_PKT_H2C_CMD_ID(h2c_pkt, value) \ argument
249 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(15, 8))
250 #define SET_PKT_H2C_SUB_CMD_ID(h2c_pkt, value) \ argument
251 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x00, value, GENMASK(31, 16))
252 #define SET_PKT_H2C_TOTAL_LEN(h2c_pkt, value) \ argument
253 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(15, 0))
262 #define FW_OFFLOAD_H2C_SET_SEQ_NUM(h2c_pkt, value) \ argument
263 le32p_replace_bits((__le32 *)(h2c_pkt) + 0x01, value, GENMASK(31, 16))
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| D | tx.h | 12 #define SET_TX_DESC_TXPKTSIZE(txdesc, value) \ argument
13 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(15, 0))
14 #define SET_TX_DESC_OFFSET(txdesc, value) \ argument
15 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, GENMASK(23, 16))
16 #define SET_TX_DESC_PKT_OFFSET(txdesc, value) \ argument
17 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(28, 24))
18 #define SET_TX_DESC_QSEL(txdesc, value) \ argument
19 le32p_replace_bits((__le32 *)(txdesc) + 0x01, value, GENMASK(12, 8))
20 #define SET_TX_DESC_BMC(txdesc, value) \ argument
21 le32p_replace_bits((__le32 *)(txdesc) + 0x00, value, BIT(24))
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| /drivers/media/pci/cx25821/ |
| D | cx25821-medusa-video.c | 24 u32 value = 0; in medusa_enable_bluefield_output() local
63 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl, &tmp); in medusa_enable_bluefield_output()
64 value &= 0xFFFFFF7F; /* clear BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
66 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
67 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl, value); in medusa_enable_bluefield_output()
69 value = cx25821_i2c_read(&dev->i2c_bus[0], out_ctrl_ns, &tmp); in medusa_enable_bluefield_output()
70 value &= 0xFFFFFF7F; in medusa_enable_bluefield_output()
72 value |= 0x00000080; /* set BLUE_FIELD_EN */ in medusa_enable_bluefield_output()
73 cx25821_i2c_write(&dev->i2c_bus[0], out_ctrl_ns, value); in medusa_enable_bluefield_output()
80 u32 value = 0; in medusa_initialize_ntsc() local
[all …]
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_opp_csc_v.c | 127 uint32_t value = 0; in program_color_matrix_v() local
131 value, in program_color_matrix_v()
137 value, in program_color_matrix_v()
142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
145 uint32_t value = 0; in program_color_matrix_v() local
149 value, in program_color_matrix_v()
155 value, in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
163 uint32_t value = 0; in program_color_matrix_v() local
167 value, in program_color_matrix_v()
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| D | dce110_opp_regamma_v.c | 39 uint32_t value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut() local
45 value, in power_on_lut()
51 value, in power_on_lut()
58 value, in power_on_lut()
64 value, in power_on_lut()
70 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
73 value = dm_read_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL); in power_on_lut()
74 if (get_reg_field_value(value, in power_on_lut()
77 get_reg_field_value(value, in power_on_lut()
88 uint32_t value; in set_bypass_input_gamma() local
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| D | dce110_timing_generator.c | 95 uint32_t value = 0; in dce110_timing_generator_is_in_vertical_blank() local
100 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
101 field = get_reg_field_value(value, CRTC_STATUS, CRTC_V_BLANK); in dce110_timing_generator_is_in_vertical_blank()
128 uint32_t value = 0; in dce110_timing_generator_enable_crtc() local
135 value, in dce110_timing_generator_enable_crtc()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
143 value = 0; in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
157 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_program_blank_color() local
160 value, in dce110_timing_generator_program_blank_color()
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| D | dce110_mem_input_v.c | 42 uint32_t value = 0; in set_flip_control() local
44 value = dm_read_reg( in set_flip_control()
48 set_reg_field_value(value, 1, in set_flip_control()
55 value); in set_flip_control()
63 uint32_t value = 0; in program_pri_addr_c() local
69 set_reg_field_value(value, temp, in program_pri_addr_c()
76 value); in program_pri_addr_c()
79 value = 0; in program_pri_addr_c()
83 set_reg_field_value(value, temp, in program_pri_addr_c()
90 value); in program_pri_addr_c()
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| D | dce110_timing_generator_v.c | 60 uint32_t value; in dce110_timing_generator_v_enable_crtc() local
62 value = 0; in dce110_timing_generator_v_enable_crtc()
63 set_reg_field_value(value, 0, in dce110_timing_generator_v_enable_crtc()
66 mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
69 value = 0; in dce110_timing_generator_v_enable_crtc()
70 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
72 value = 0; in dce110_timing_generator_v_enable_crtc()
73 set_reg_field_value(value, 1, in dce110_timing_generator_v_enable_crtc()
76 mmCRTCV_MASTER_EN, value); in dce110_timing_generator_v_enable_crtc()
83 uint32_t value; in dce110_timing_generator_v_disable_crtc() local
[all …]
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| /drivers/video/fbdev/riva/ |
| D | nvreg.h | 34 #define SetBF(mask,value) ((value) << (0?mask)) argument
37 #define MaskAndSetBF(var,mask,value) (var)=(((var)&(~MASKEXPAND(mask)) \ argument
38 | SetBF(mask,value)))
47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument
51 #define DEVICE_DEF(device,mask,value) \ argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
53 #define DEVICE_VALUE(device,mask,value) SetBF(NV_##device##_##mask,value) argument
56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument
59 #define PDAC_Def(mask,value) DEVICE_DEF(PDAC,mask,value) argument
60 #define PDAC_Val(mask,value) DEVICE_VALUE(PDAC,mask,value) argument
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| /drivers/gpu/drm/amd/display/include/ |
| D | fixed31_32.h | 58 long long value; member
97 res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART; in dc_fixpt_from_int()
115 res.value = -arg.value; in dc_fixpt_neg()
126 if (arg.value < 0) in dc_fixpt_abs()
143 return arg1.value < arg2.value; in dc_fixpt_lt()
152 return arg1.value <= arg2.value; in dc_fixpt_le()
161 return arg1.value == arg2.value; in dc_fixpt_eq()
170 if (arg1.value <= arg2.value) in dc_fixpt_min()
182 if (arg1.value <= arg2.value) in dc_fixpt_max()
218 ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || in dc_fixpt_shl()
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| /drivers/phy/tegra/ |
| D | xusb-tegra210.c | 264 u32 value; in tegra210_pex_uphy_enable() local
280 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
281 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK << in tegra210_pex_uphy_enable()
283 value |= XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_VAL << in tegra210_pex_uphy_enable()
285 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL2); in tegra210_pex_uphy_enable()
287 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
288 value &= ~(XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_MASK << in tegra210_pex_uphy_enable()
290 value |= XUSB_PADCTL_UPHY_PLL_CTL5_DCO_CTRL_VAL << in tegra210_pex_uphy_enable()
292 padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL5); in tegra210_pex_uphy_enable()
294 value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1); in tegra210_pex_uphy_enable()
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| D | xusb-tegra124.c | 227 u32 value; in tegra124_xusb_padctl_enable() local
234 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
235 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN; in tegra124_xusb_padctl_enable()
236 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
240 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
241 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY; in tegra124_xusb_padctl_enable()
242 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
246 value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
247 value &= ~XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN; in tegra124_xusb_padctl_enable()
248 padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM); in tegra124_xusb_padctl_enable()
[all …]
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| /drivers/net/ethernet/stmicro/stmmac/ |
| D | dwxgmac2_dma.c | 13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset() local
16 writel(value | XGMAC_SWR, ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
18 return readl_poll_timeout(ioaddr + XGMAC_DMA_MODE, value, in dwxgmac2_dma_reset()
19 !(value & XGMAC_SWR), 0, 100000); in dwxgmac2_dma_reset()
25 u32 value = readl(ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init() local
28 value |= XGMAC_AAL; in dwxgmac2_dma_init()
31 value |= XGMAC_EAME; in dwxgmac2_dma_init()
33 writel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE); in dwxgmac2_dma_init()
39 u32 value = readl(ioaddr + XGMAC_DMA_CH_CONTROL(chan)); in dwxgmac2_dma_init_chan() local
42 value |= XGMAC_PBLx8; in dwxgmac2_dma_init_chan()
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| D | dwmac4_core.c | 27 u32 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_core_init() local
29 value |= GMAC_CORE_INIT; in dwmac4_core_init()
32 value |= GMAC_CONFIG_TE; in dwmac4_core_init()
34 value &= hw->link.speed_mask; in dwmac4_core_init()
37 value |= hw->link.speed1000; in dwmac4_core_init()
40 value |= hw->link.speed100; in dwmac4_core_init()
43 value |= hw->link.speed10; in dwmac4_core_init()
48 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_core_init()
51 value = GMAC_INT_DEFAULT_ENABLE; in dwmac4_core_init()
54 value |= GMAC_PCS_IRQ_DEFAULT; in dwmac4_core_init()
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| D | dwxgmac2_core.c | 70 u32 value; in dwxgmac2_rx_ipc() local
72 value = readl(ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
74 value |= XGMAC_CONFIG_IPC; in dwxgmac2_rx_ipc()
76 value &= ~XGMAC_CONFIG_IPC; in dwxgmac2_rx_ipc()
77 writel(value, ioaddr + XGMAC_RX_CONFIG); in dwxgmac2_rx_ipc()
86 u32 value; in dwxgmac2_rx_queue_enable() local
88 value = readl(ioaddr + XGMAC_RXQ_CTRL0) & ~XGMAC_RXQEN(queue); in dwxgmac2_rx_queue_enable()
90 value |= 0x1 << XGMAC_RXQEN_SHIFT(queue); in dwxgmac2_rx_queue_enable()
92 value |= 0x2 << XGMAC_RXQEN_SHIFT(queue); in dwxgmac2_rx_queue_enable()
93 writel(value, ioaddr + XGMAC_RXQ_CTRL0); in dwxgmac2_rx_queue_enable()
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| /drivers/gpu/drm/amd/display/dc/dce/ |
| D | dce_scl_filters.c | 1343 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_16p()
1345 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_16p()
1347 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_16p()
1355 if (ratio.value < dc_fixpt_one.value) in get_filter_3tap_64p()
1357 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_3tap_64p()
1359 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_3tap_64p()
1367 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_16p()
1369 else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) in get_filter_4tap_16p()
1371 else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) in get_filter_4tap_16p()
1379 if (ratio.value < dc_fixpt_one.value) in get_filter_4tap_64p()
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| D | dce_audio.c | 54 #define AZ_REG_WRITE(reg_name, value) \ argument
55 write_indirect_azalia_reg(audio, IX_REG(reg_name), value)
79 uint32_t value = 0; in read_indirect_azalia_reg() local
86 value = REG_READ(AZALIA_F0_CODEC_ENDPOINT_DATA); in read_indirect_azalia_reg()
89 reg_index, value); in read_indirect_azalia_reg()
91 return value; in read_indirect_azalia_reg()
299 uint32_t value = 0; in set_high_bit_rate_capable() local
302 value = AZ_REG_READ(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR); in set_high_bit_rate_capable()
304 set_reg_field_value(value, capable, in set_high_bit_rate_capable()
308 AZ_REG_WRITE(AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR, value); in set_high_bit_rate_capable()
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| /drivers/gpu/drm/i915/ |
| D | i915_getparam.c | 17 int value; in i915_getparam_ioctl() local
27 value = i915->drm.pdev->device; in i915_getparam_ioctl()
30 value = i915->drm.pdev->revision; in i915_getparam_ioctl()
33 value = i915->ggtt.num_fences; in i915_getparam_ioctl()
36 value = !!i915->overlay; in i915_getparam_ioctl()
39 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
43 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
47 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
51 value = !!intel_engine_lookup_user(i915, in i915_getparam_ioctl()
55 value = HAS_LLC(i915); in i915_getparam_ioctl()
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| /drivers/gpu/drm/tegra/ |
| D | sor.c | 486 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
488 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
490 return value; in tegra_sor_readl()
493 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
496 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
497 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
544 u32 value; in tegra_clk_sor_pad_set_parent() local
546 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
547 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
551 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
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| /drivers/net/ethernet/sfc/falcon/ |
| D | io.h | 67 static inline void _ef4_writeq(struct ef4_nic *efx, __le64 value, in _ef4_writeq() argument
70 __raw_writeq((__force u64)value, efx->membase + reg); in _ef4_writeq()
78 static inline void _ef4_writed(struct ef4_nic *efx, __le32 value, in _ef4_writed() argument
81 __raw_writel((__force u32)value, efx->membase + reg); in _ef4_writed()
89 static inline void ef4_writeo(struct ef4_nic *efx, const ef4_oword_t *value, in ef4_writeo() argument
96 EF4_OWORD_VAL(*value)); in ef4_writeo()
100 _ef4_writeq(efx, value->u64[0], reg + 0); in ef4_writeo()
101 _ef4_writeq(efx, value->u64[1], reg + 8); in ef4_writeo()
103 _ef4_writed(efx, value->u32[0], reg + 0); in ef4_writeo()
104 _ef4_writed(efx, value->u32[1], reg + 4); in ef4_writeo()
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| /drivers/net/ethernet/sfc/ |
| D | io.h | 84 static inline void _efx_writeq(struct efx_nic *efx, __le64 value, in _efx_writeq() argument
87 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq()
95 static inline void _efx_writed(struct efx_nic *efx, __le32 value, in _efx_writed() argument
98 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed()
106 static inline void efx_writeo(struct efx_nic *efx, const efx_oword_t *value, in efx_writeo() argument
113 EFX_OWORD_VAL(*value)); in efx_writeo()
117 _efx_writeq(efx, value->u64[0], reg + 0); in efx_writeo()
118 _efx_writeq(efx, value->u64[1], reg + 8); in efx_writeo()
120 _efx_writed(efx, value->u32[0], reg + 0); in efx_writeo()
121 _efx_writed(efx, value->u32[1], reg + 4); in efx_writeo()
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | bw_fixed.h | 33 int64_t value; member
45 return (arg1.value <= arg2.value) ? arg1 : arg2; in bw_min2()
51 return (arg2.value <= arg1.value) ? arg1 : arg2; in bw_max2()
68 struct bw_fixed bw_int_to_fixed_nonconst(int64_t value);
69 static inline struct bw_fixed bw_int_to_fixed(int64_t value) in bw_int_to_fixed() argument
71 if (__builtin_constant_p(value)) { in bw_int_to_fixed()
73 BUILD_BUG_ON(value > BW_FIXED_MAX_I32 || value < BW_FIXED_MIN_I32); in bw_int_to_fixed()
74 res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART; in bw_int_to_fixed()
77 return bw_int_to_fixed_nonconst(value); in bw_int_to_fixed()
80 static inline int32_t bw_fixed_to_int(struct bw_fixed value) in bw_fixed_to_int() argument
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| /drivers/media/usb/cx231xx/ |
| D | cx231xx-avcore.c | 65 u32 value = 0; in initGPIO() local
70 cx231xx_send_gpio_cmd(dev, _gpio_direction, (u8 *)&value, 4, 0, 0); in initGPIO()
86 u8 value[4] = { 0, 0, 0, 0 }; in uninitGPIO() local
91 0x68, value, 4); in uninitGPIO()
262 u8 value = 0; in cx231xx_afe_set_input_mux() local
265 status = afe_read_byte(dev, ADC_INPUT_CH1, &value); in cx231xx_afe_set_input_mux()
266 value &= ~INPUT_SEL_MASK; in cx231xx_afe_set_input_mux()
267 value |= (ch1_setting - 1) << 4; in cx231xx_afe_set_input_mux()
268 value &= 0xff; in cx231xx_afe_set_input_mux()
269 status = afe_write_byte(dev, ADC_INPUT_CH1, value); in cx231xx_afe_set_input_mux()
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| /drivers/infiniband/hw/bnxt_re/ |
| D | hw_counters.c | 126 stats->value[BNXT_RE_ACTIVE_QP] = atomic_read(&rdev->qp_count); in bnxt_re_ib_get_hw_stats()
127 stats->value[BNXT_RE_ACTIVE_SRQ] = atomic_read(&rdev->srq_count); in bnxt_re_ib_get_hw_stats()
128 stats->value[BNXT_RE_ACTIVE_CQ] = atomic_read(&rdev->cq_count); in bnxt_re_ib_get_hw_stats()
129 stats->value[BNXT_RE_ACTIVE_MR] = atomic_read(&rdev->mr_count); in bnxt_re_ib_get_hw_stats()
130 stats->value[BNXT_RE_ACTIVE_MW] = atomic_read(&rdev->mw_count); in bnxt_re_ib_get_hw_stats()
132 stats->value[BNXT_RE_RECOVERABLE_ERRORS] = in bnxt_re_ib_get_hw_stats()
134 stats->value[BNXT_RE_RX_DROPS] = in bnxt_re_ib_get_hw_stats()
136 stats->value[BNXT_RE_RX_DISCARDS] = in bnxt_re_ib_get_hw_stats()
138 stats->value[BNXT_RE_RX_PKTS] = in bnxt_re_ib_get_hw_stats()
140 stats->value[BNXT_RE_RX_BYTES] = in bnxt_re_ib_get_hw_stats()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | bw_fixed.c | 49 struct bw_fixed bw_int_to_fixed_nonconst(int64_t value) in bw_int_to_fixed_nonconst() argument
52 ASSERT(value < BW_FIXED_MAX_I32 && value > BW_FIXED_MIN_I32); in bw_int_to_fixed_nonconst()
53 res.value = value << BW_FIXED_BITS_PER_FRACTIONAL_PART; in bw_int_to_fixed_nonconst()
104 res.value = (int64_t)(res_value); in bw_frc_to_fixed()
107 res.value = -res.value; in bw_frc_to_fixed()
118 multiplicand = div64_s64(arg.value, abs_i64(significance.value)); in bw_floor2()
119 result.value = abs_i64(significance.value) * multiplicand; in bw_floor2()
120 ASSERT(abs_i64(result.value) <= abs_i64(arg.value)); in bw_floor2()
131 multiplicand = div64_s64(arg.value, abs_i64(significance.value)); in bw_ceil2()
132 result.value = abs_i64(significance.value) * multiplicand; in bw_ceil2()
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