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Searched refs:vert (Results 1 – 16 of 16) sorted by relevance

/drivers/media/platform/omap3isp/
Dispresizer.c317 rgval |= ((ratio->vert - 1) << ISPRSZ_CNT_VRSZ_SHIFT) in resizer_set_ratio()
328 if (ratio->vert > MID_RESIZE_VALUE) in resizer_set_ratio()
805 ratio->vert = ((input->height - 4) * 256 + 255 - 16 - 32 * spv) in resizer_calc_ratios()
807 if (ratio->vert > MID_RESIZE_VALUE) in resizer_calc_ratios()
808 ratio->vert = ((input->height - 7) * 256 + 255 - 32 - 64 * spv) in resizer_calc_ratios()
810 ratio->vert = clamp_t(unsigned int, ratio->vert, in resizer_calc_ratios()
813 if (ratio->vert <= MID_RESIZE_VALUE) { in resizer_calc_ratios()
814 upscaled_height = (output->height - 1) * ratio->vert in resizer_calc_ratios()
818 upscaled_height = (output->height - 1) * ratio->vert in resizer_calc_ratios()
830 if (ratio->vert <= MID_RESIZE_VALUE) { in resizer_calc_ratios()
[all …]
Dispresizer.h61 u32 vert; member
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_dpp_dscl.c181 && data->ratios.vert.value == one in dpp1_dscl_get_dscl_mode()
193 if (data->ratios.horz.value == one && data->ratios.vert.value == one) in dpp1_dscl_get_dscl_mode()
306 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp1_dscl_set_scl_filter()
337 scl_data->taps.v_taps, scl_data->ratios.vert); in dpp1_dscl_set_scl_filter()
483 int ceil_vratio = dc_fixpt_ceil(scl_data->ratios.vert); in dpp1_dscl_find_lb_memory_config()
590 SCL_V_SCALE_RATIO, dc_fixpt_u3d19(data->ratios.vert) << 5); in dpp1_dscl_set_manual_ratio_init()
Ddcn10_dpp.c141 scl_data->ratios.vert.value != dc_fixpt_one.value) in dpp1_get_optimal_number_of_taps()
154 if (scl_data->ratios.vert.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
155 scl_data->ratios.vert.value--; in dpp1_get_optimal_number_of_taps()
185 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp1_get_optimal_number_of_taps()
Ddcn10_hw_sequencer.c3391 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dcn10_set_cursor_position()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_transform.c288 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
302 data->ratios.vert, in calculate_inits()
320 dc_fixpt_u2d19(data->ratios.vert) << 5; in dce60_calculate_inits()
331 data->ratios.vert, in dce60_calculate_inits()
439 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce_transform_set_scaler()
525 coeffs_v = get_filter_coeffs_16p(data->taps.v_taps, data->ratios.vert); in dce60_transform_set_scaler()
1208 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps()
1212 if (!IDENTITY_RATIO(scl_data->ratios.vert)) { in dce_transform_get_optimal_number_of_taps()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dtransform.h143 struct fixed31_32 vert; member
150 int vert; member
/drivers/media/platform/davinci/
Disif.c356 (bc->vert.reset_val_sel << ISIF_VERT_BC_RST_VAL_SEL_SHIFT) | in isif_config_bclamp()
357 (bc->vert.line_ave_coef << ISIF_VERT_BC_LINE_AVE_COEF_SHIFT); in isif_config_bclamp()
361 regw(bc->vert.ob_start_h, CLVWIN1); in isif_config_bclamp()
363 regw(bc->vert.ob_start_v, CLVWIN2); in isif_config_bclamp()
365 regw(bc->vert.ob_v_sz_calc, CLVWIN3); in isif_config_bclamp()
/drivers/gpu/drm/amd/display/dc/dcn30/
Ddcn30_dpp.c413 if (dc_fixpt_ceil(scl_data->ratios.vert) > 1) in dpp3_get_optimal_number_of_taps()
414 scl_data->taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int(scl_data->ratios.vert, 2)), 8); in dpp3_get_optimal_number_of_taps()
438 min_taps_y = dc_fixpt_ceil(scl_data->ratios.vert); in dpp3_get_optimal_number_of_taps()
451 if (dc_fixpt_ceil(scl_data->ratios.vert) > 2) in dpp3_get_optimal_number_of_taps()
452 max_taps_y = num_part_y - (dc_fixpt_ceil(scl_data->ratios.vert) - 2); in dpp3_get_optimal_number_of_taps()
475 if (IDENTITY_RATIO(scl_data->ratios.vert)) in dpp3_get_optimal_number_of_taps()
/drivers/gpu/drm/amd/display/dc/core/
Ddc_resource.c853 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_from_fraction( in calculate_scaling_ratios()
860 pipe_ctx->plane_res.scl_data.ratios.vert.value *= 2; in calculate_scaling_ratios()
862 pipe_ctx->plane_res.scl_data.ratios.vert.value = div64_s64( in calculate_scaling_ratios()
863 pipe_ctx->plane_res.scl_data.ratios.vert.value * in_h, out_h); in calculate_scaling_ratios()
868 pipe_ctx->plane_res.scl_data.ratios.vert_c = pipe_ctx->plane_res.scl_data.ratios.vert; in calculate_scaling_ratios()
877 pipe_ctx->plane_res.scl_data.ratios.vert = dc_fixpt_truncate( in calculate_scaling_ratios()
878 pipe_ctx->plane_res.scl_data.ratios.vert, 19); in calculate_scaling_ratios()
1038 dc_fixpt_add_int(data->ratios.vert, data->taps.v_taps + 1), 2), 19); in calculate_inits_and_adj_vp()
1052 orthogonal_rotation ? data->ratios.vert : data->ratios.horz, in calculate_inits_and_adj_vp()
1070 orthogonal_rotation ? data->ratios.horz : data->ratios.vert, in calculate_inits_and_adj_vp()
[all …]
/drivers/gpu/drm/amd/display/dc/dce110/
Ddce110_transform_v.c380 dc_fixpt_u2d19(data->ratios.vert) << 5; in calculate_inits()
562 coeffs_v = get_filter_coeffs_64p(data->taps.v_taps, data->ratios.vert); in dce110_xfmv_set_scaler()
Ddce110_hw_sequencer.c2755 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, in dce110_set_cursor_position()
/drivers/gpu/ipu-v3/
Dipu-csi.c589 void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert) in ipu_csi_set_downsize() argument
599 (vert ? CSI_VERT_DOWNSIZE_EN : 0); in ipu_csi_set_downsize()
/drivers/gpu/drm/amd/display/dc/calcs/
Ddcn_calcs.c400 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
997 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()
1002 ASSERT(pipe->plane_res.scl_data.ratios.vert.value != dc_fixpt_one.value in dcn_validate_bandwidth()
Ddce_calcs.c2805 …ale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); in populate_initial_data()
2862 pipe[i].bottom_pipe->plane_res.scl_data.ratios.vert.value); in populate_initial_data()
2907 …ale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.vert.value); in populate_initial_data()
/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_resource.c2336 pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2339 scl->ratios.vert.value != dc_fixpt_one.value