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Searched refs:viafb_write_reg_mask (Results 1 – 6 of 6) sorted by relevance

/drivers/video/fbdev/via/
Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); in viafb_tmds_trasmitter_identify()
61 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 + in viafb_tmds_trasmitter_identify()
66 viafb_write_reg_mask(SR3E, VIASR, 0x0, BIT5); in viafb_tmds_trasmitter_identify()
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0()
326 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4); in dvi_patch_skew_dvp0()
334 viafb_write_reg_mask(CR96, VIACR, 0x03, in dvi_patch_skew_dvp0()
337 viafb_write_reg_mask(CR96, VIACR, 0x07, in dvi_patch_skew_dvp0()
344 viafb_write_reg_mask(CR96, VIACR, 0x07, in dvi_patch_skew_dvp0()
[all …]
Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
376 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); in load_lcd_scaling()
388 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7); in load_lcd_scaling()
420 viafb_write_reg_mask(CRA2, VIACR, 0x08, BIT3); in load_lcd_scaling()
432 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT3); in load_lcd_scaling()
519 viafb_write_reg_mask(CR99, VIACR, 0x08, in lcd_patch_skew()
585 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
608 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable()
611 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); in integrated_lvds_disable()
617 viafb_write_reg_mask(CR6A, VIACR, 0, BIT3); in integrated_lvds_disable()
[all …]
Dhw.c466 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); in viafb_lock_crt()
471 viafb_write_reg_mask(CR11, VIACR, 0, BIT7); in viafb_unlock_crt()
472 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
668 viafb_write_reg_mask(0x1A, VIASR, 0x00, 0x01); in viafb_set_primary_color_register()
674 viafb_write_reg_mask(0x1A, VIASR, 0x01, 0x01); in viafb_set_secondary_color_register()
945 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); in load_fix_bit_crtc_reg()
947 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4); in load_fix_bit_crtc_reg()
949 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
957 viafb_write_reg_mask(CR33, VIACR, 0x08, BIT3); in load_fix_bit_crtc_reg()
960 viafb_write_reg_mask(SR1A, VIASR, 0x02, BIT1); in load_fix_bit_crtc_reg()
[all …]
Dvia_utility.c138 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_set_gamma_table()
148 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); in viafb_set_gamma_table()
152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
170 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
193 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); in viafb_get_gamma_table()
203 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); in viafb_get_gamma_table()
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
Dviafbdev.c1151 viafb_write_reg_mask(CR96, VIACR, in viafb_dvp0_proc_write()
1155 viafb_write_reg_mask(SR2A, VIASR, in viafb_dvp0_proc_write()
1157 viafb_write_reg_mask(SR1B, VIASR, in viafb_dvp0_proc_write()
1161 viafb_write_reg_mask(SR2A, VIASR, in viafb_dvp0_proc_write()
1163 viafb_write_reg_mask(SR1E, VIASR, in viafb_dvp0_proc_write()
1219 viafb_write_reg_mask(CR9B, VIACR, in viafb_dvp1_proc_write()
1223 viafb_write_reg_mask(SR65, VIASR, in viafb_dvp1_proc_write()
1227 viafb_write_reg_mask(SR65, VIASR, in viafb_dvp1_proc_write()
1270 viafb_write_reg_mask(CR97, VIACR, reg_val, 0x0f); in viafb_dfph_proc_write()
1304 viafb_write_reg_mask(CR99, VIACR, reg_val, 0x0f); in viafb_dfpl_proc_write()
Dhw.h19 #define viafb_write_reg_mask(i, p, d, m) via_write_reg_mask(p, i, d, m) macro