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Searched refs:vsync_pulse_width (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_intf.c97 vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height + in dpu_hw_intf_setup_timing_engine()
100 display_v_start = ((p->vsync_pulse_width + p->v_back_porch) * in dpu_hw_intf_setup_timing_engine()
180 p->vsync_pulse_width * hsync_period); in dpu_hw_intf_setup_timing_engine()
Ddpu_encoder_phys_vid.c79 timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start; in drm_mode_to_intf_timing_params()
127 timing->vsync_pulse_width; in get_vertical_total()
152 timing->v_back_porch + timing->vsync_pulse_width; in programmable_fetch_get_num_lines()
176 timing->vsync_pulse_width); in programmable_fetch_get_num_lines()
Ddpu_hw_intf.h27 u32 vsync_pulse_width; member
/drivers/gpu/drm/gma500/
Dintel_bios.h303 u8 vsync_pulse_width:4; member
Dintel_bios.c163 dvo_timing->vsync_pulse_width; in fill_detail_timing_data()
/drivers/gpu/drm/
Ddrm_edid.c2626 …unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offse… in drm_mode_detailed() local
2641 if (!hsync_pulse_width || !vsync_pulse_width) { in drm_mode_detailed()
2671 mode->vsync_end = mode->vsync_start + vsync_pulse_width; in drm_mode_detailed()