/drivers/staging/rtl8723bs/include/ |
D | hal_pwr_seq.h | 50 … PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x… 58 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable fallin… 59 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 … 60 …{0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1… 62 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR … 71 …{0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1… 73 …K, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, /*0x04[9] = 1 … 74 …SK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, /*wait till 0x… 89 …, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, /*wait power s… 96 …WR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, /*wait power s… [all …]
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D | hal_com_reg.h | 609 #define RRSR_2M BIT1 634 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1 728 #define BW_OPMODE_5G BIT1 760 #define WOW_WOMEN BIT1 /* WoW function on or off. */ 803 #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */ 814 #define IMR_OCPINT BIT1 851 #define PHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ 869 #define PHIMR_OCPINT BIT1 902 #define UHIMR_RDU BIT1 /* Receive Descriptor Unavailable */ 922 #define UHIMR_OCPINT BIT1 [all …]
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D | rtw_ht.h | 69 #define LDPC_HT_ENABLE_TX BIT1 74 #define STBC_HT_ENABLE_TX BIT1 79 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
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D | rtl8723b_spec.h | 225 #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
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D | hal_phy.h | 39 #define ANT_DETECT_BY_RSSI BIT1
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D | osdep_service.h | 22 #define BIT1 0x00000002 macro
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/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
D | pwrseq.h | 29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \ 57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 69 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \ 170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \ 288 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \ 294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0 \ [all …]
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/drivers/scsi/ |
D | dc395x.h | 75 #define BIT1 0x00000002 macro 80 #define UNIT_INFO_CHANGED BIT1 86 #define SCSI_SUPPORT BIT1 122 #define RESET_DETECT BIT1 130 #define ABORTION BIT1 142 #define ABORT_DEV BIT1 175 #define SYNC_NEGO_DONE BIT1 631 #define GREATER_1G BIT1
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/drivers/staging/rtl8192e/rtl8192e/ |
D | r8192E_hw.h | 130 #define RCR_FILTER_MASK (BIT0 | BIT1 | BIT2 | BIT3 | BIT5 | BIT12 | \ 148 #define RCR_APM BIT1 202 #define SCR_RxUseDK BIT1 227 #define IMR_VODOK BIT1 232 #define TPPoll_BEQ BIT1 272 #define AcmHw_BeqEn BIT1 280 #define AcmFw_ViqStatus BIT1 333 #define BW_OPMODE_5G BIT1 362 #define RRSR_2M BIT1
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/drivers/video/fbdev/via/ |
D | dvi.c | 45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify() 52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify() 325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1); in dvi_patch_skew_dvp0() 335 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0() 338 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0() 345 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0() 346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1); in dvi_patch_skew_dvp0() 363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low() 370 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low() 377 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
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D | lcd.c | 345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling() 520 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew() 563 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode() 608 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1); in integrated_lvds_disable() 652 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable() 654 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable() 674 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1); in integrated_lvds_enable() 746 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
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D | via_utility.c | 170 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1); in viafb_set_gamma_table()
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/drivers/staging/rtl8723bs/hal/ |
D | odm_DIG.h | 93 ODM_RESUME_DIG = BIT1 98 ODM_RESUME_CCKPD = BIT1
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D | odm.h | 420 ODM_BB_RA_MASK = BIT1, 483 ODM_RF_TX_B = BIT1, 529 ODM_LINK = BIT1, 543 ODM_WM_G = BIT1,
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D | odm_debug.h | 62 #define ODM_COMP_RA_MASK BIT1
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D | HalHWImg8723B_MAC.c | 100 if ((cond1 & BIT1) != 0) /* GPA */ in CheckPositive()
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D | HalBtc8723b2Ant.h | 14 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
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D | HalBtcOutSrc.h | 94 #define ALGO_WIFI_RSSI_STATE BIT1 106 #define WIFI_AP_CONNECTED BIT1
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/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
D | halbt_precomp.h | 32 #define BIT1 0x00000002 macro
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D | halbtc8821a1ant.h | 14 #define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
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D | halbtc8192e2ant.h | 13 #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
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D | halbtc8821a2ant.h | 14 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
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D | halbtc8723b2ant.h | 16 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
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/drivers/tty/ |
D | synclink_gt.c | 194 #define desc_crc_error(a) (le16_to_cpu((a).status) & BIT1) 355 #define MASK_PARITY BIT1 1791 status = *(p + 1) & (BIT1 + BIT0); in rx_async() 1793 if (status & BIT1) in rx_async() 1800 if (status & BIT1) in rx_async() 1978 if (status & BIT1) { in dcd_change() 3814 wr_reg32(info, RDCSR, BIT1); in rdma_reset() 3827 wr_reg32(info, TDCSR, BIT1); in tdma_reset() 3891 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_stop() 3916 val = rd_reg16(info, RCR) & ~BIT1; /* clear enable bit */ in rx_start() [all …]
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/drivers/staging/rtl8192e/ |
D | rtl819x_Qos.h | 11 #define BIT1 0x00000002 macro
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