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Searched refs:MC_SEQ_WR_CTL_D1 (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/radeon/
Dbtcd.h112 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
Dbtc_dpm.c1881 case MC_SEQ_WR_CTL_D1 >> 2: in btc_check_s0_mc_reg_index()
2037 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in btc_initialize_mc_reg_table()
Dnid.h788 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
Dsid.h549 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
Dcikd.h662 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
Devergreend.h294 #define MC_SEQ_WR_CTL_D1 0x28c0 macro
Dci_dpm.c4436 case MC_SEQ_WR_CTL_D1 >> 2: in ci_check_s0_mc_reg_index()
4554 case MC_SEQ_WR_CTL_D1: in ci_register_patching_mc_seq()
4635 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in ci_initialize_mc_reg_table()
Dni_dpm.c2796 case MC_SEQ_WR_CTL_D1 >> 2: in ni_check_s0_mc_reg_index()
2893 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in ni_initialize_mc_reg_table()
Dcypress_dpm.c1005 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_WR_CTL_D1 >> 2; in cypress_set_mc_reg_address_table()
Dsi_dpm.c5434 case MC_SEQ_WR_CTL_D1 >> 2: in si_check_s0_mc_reg_index()
5535 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in si_initialize_mc_reg_table()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h550 #define MC_SEQ_WR_CTL_D1 0xA30 macro
/drivers/gpu/drm/amd/pm/powerplay/
Dsi_dpm.c5885 case MC_SEQ_WR_CTL_D1: in si_check_s0_mc_reg_index()
5986 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); in si_initialize_mc_reg_table()