Home
last modified time | relevance | path

Searched refs:PLL_CTL0_EN (Results 1 – 1 of 1) sorted by relevance

/drivers/net/mdio/
Dmdio-mux-meson-g12a.c22 #define PLL_CTL0_EN BIT(28) macro
90 val |= PLL_CTL0_RST | PLL_CTL0_EN; in g12a_ephy_pll_enable()
112 val &= ~PLL_CTL0_EN; in g12a_ephy_pll_disable()