Home
last modified time | relevance | path

Searched refs:REG_DSI_10nm_PHY_CMN_PLL_CNTRL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/msm/dsi/phy/
Ddsi_phy_10nm.c16 data = dsi_phy_read(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL); in dsi_phy_hw_v3_0_is_pll_on()
123 dsi_phy_write(base + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0x00); in dsi_10nm_phy_enable()
/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_10nm.c421 pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, in dsi_pll_10nm_vco_prepare()
470 pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0); in dsi_pll_10nm_vco_unprepare()
/drivers/gpu/drm/msm/dsi/
Ddsi.xml.h1747 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038 macro