Searched refs:REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 (Results 1 – 2 of 2) sorted by relevance
538 pll_write(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3, data); in pll_db_commit_14nm()640 div_frac_start = (pll_read(base + REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3) in dsi_pll_14nm_vco_recalc_rate()
1695 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc macro