Searched refs:REG_DSI_28nm_PHY_PLL_TEST_CFG (Results 1 – 2 of 2) sorted by relevance
119 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, in pll_28nm_software_reset()121 pll_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset()
1229 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068 macro