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Searched refs:SDMA0_BASE__INST5_SEG0 (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/amd/include/
Dvega20_ip_offset.h707 #define SDMA0_BASE__INST5_SEG0 0 macro
Dsienna_cichlid_ip_offset.h904 #define SDMA0_BASE__INST5_SEG0 0 macro
Drenoir_ip_offset.h1147 #define SDMA0_BASE__INST5_SEG0 0 macro
Darct_ip_offset.h953 #define SDMA0_BASE__INST5_SEG0 0 macro