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Searched refs:WREG32_UVD_CTX (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c226 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); in uvd_v3_1_set_dcm()
365 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); in uvd_v3_1_start()
601 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
610 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v3_1_enable_mgcg()
Duvd_v4_2.c301 WREG32_UVD_CTX(ixUVD_LMI_CACHE_CTRL, tmp & (~0x10)); in uvd_v4_2_start()
582 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
591 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v4_2_enable_mgcg()
624 WREG32_UVD_CTX(ixUVD_CGC_CTRL2, tmp2); in uvd_v4_2_set_dcm()
Duvd_v5_0.c742 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
751 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v5_0_enable_mgcg()
Damdgpu_cgs.c96 return WREG32_UVD_CTX(index, value); in amdgpu_cgs_write_ind_register()
Duvd_v6_0.c1405 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
1414 WREG32_UVD_CTX(ixUVD_CGC_MEM_CTRL, data); in uvd_v6_0_enable_mgcg()
Damdgpu.h1083 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v)) macro
/drivers/gpu/drm/radeon/
Dsi.c5193 WREG32_UVD_CTX(UVD_CGC_CTRL2, tmp2); in si_set_uvd_dcm()
5463 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp); in si_enable_uvd_mgcg()
5475 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, tmp); in si_enable_uvd_mgcg()
Dradeon.h2545 #define WREG32_UVD_CTX(reg, v) r600_uvd_ctx_wreg(rdev, (reg), (v)) macro
Dcik.c6221 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data); in cik_enable_uvd_mgcg()
6230 WREG32_UVD_CTX(UVD_CGC_MEM_CTRL, data); in cik_enable_uvd_mgcg()