Searched refs:cfgPSWUSCFG0_CACHE_LINE (Results 1 – 2 of 2) sorted by relevance
| /drivers/gpu/drm/amd/include/asic_reg/nbio/ | ||
| D | nbio_6_1_offset.h | 36 #define cfgPSWUSCFG0_CACHE_LINE … macro |
| D | nbio_7_4_offset.h | 36 #define cfgPSWUSCFG0_CACHE_LINE … macro |