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Searched refs:cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/nbio/
Dnbio_6_1_offset.h122 #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL … macro
Dnbio_7_4_offset.h122 #define cfgPSWUSCFG0_PCIE_LANE_2_EQUALIZATION_CNTL … macro