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Searched refs:mmDCP0_INPUT_GAMMA_CONTROL (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/dce/
Ddce_6_0_d.h1566 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1A10 macro
Ddce_8_0_d.h1641 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 macro
Ddce_11_0_d.h2384 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 macro
Ddce_10_0_d.h2490 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 macro
Ddce_11_2_d.h3615 #define mmDCP0_INPUT_GAMMA_CONTROL 0x1a10 macro
Ddce_12_0_offset.h3560 #define mmDCP0_INPUT_GAMMA_CONTROL … macro