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Searched refs:mmUVD_RB_BASE_HI3 (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h59 #define mmUVD_RB_BASE_HI3 0x3d1e macro
Duvd_7_0_offset.h134 #define mmUVD_RB_BASE_HI3 macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h294 #define mmUVD_RB_BASE_HI3 macro
Dvcn_2_5_offset.h573 #define mmUVD_RB_BASE_HI3 macro
Dvcn_2_0_0_offset.h484 #define mmUVD_RB_BASE_HI3 macro
Dvcn_3_0_0_offset.h903 #define mmUVD_RB_BASE_HI3 macro