Home
last modified time | relevance | path

Searched refs:mmUVD_RB_BASE_LO (Results 1 – 12 of 12) sorted by relevance

/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h44 #define mmUVD_RB_BASE_LO 0x3c26 macro
Duvd_7_0_offset.h94 #define mmUVD_RB_BASE_LO … macro
/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h216 #define mmUVD_RB_BASE_LO … macro
Dvcn_2_5_offset.h551 #define mmUVD_RB_BASE_LO … macro
Dvcn_2_0_0_offset.h928 #define mmUVD_RB_BASE_LO … macro
Dvcn_3_0_0_offset.h881 #define mmUVD_RB_BASE_LO … macro
/drivers/gpu/drm/amd/amdgpu/
Dvcn_v2_5.c1090 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_start()
1261 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO), in vcn_v2_5_sriov_start()
1439 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_5_pause_dpg_mode()
Dvcn_v2_0.c1087 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_start()
1237 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v2_0_pause_dpg_mode()
1944 SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), in vcn_v2_0_start_sriov()
Dvcn_v3_0.c1200 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_start()
1335 mmUVD_RB_BASE_LO), in vcn_v3_0_start_sriov()
1572 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v3_0_pause_dpg_mode()
Duvd_v7_0.c900 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr); in uvd_v7_0_sriov_start()
1095 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v7_0_start()
Dvcn_v1_0.c946 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_start_spg_mode()
1246 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr); in vcn_v1_0_pause_dpg_mode()
Duvd_v6_0.c847 WREG32(mmUVD_RB_BASE_LO, ring->gpu_addr); in uvd_v6_0_start()