| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | display_rq_dlg_calc_30.c | 46 unsigned int odm_combine, in get_refcyc_per_delivery() argument
57 if (odm_combine) in get_refcyc_per_delivery()
58 refcyc_per_delivery = (double)refclk_freq_in_mhz * (double)((unsigned int)odm_combine*2) in get_refcyc_per_delivery()
59 * dml_min((double)recout_width, (double)hactive / ((unsigned int)odm_combine*2)) in get_refcyc_per_delivery()
777 if (pipe_param->dest.odm_combine) { in get_surf_rq_param()
783 hactive_odm = pipe_param->dest.hactive / ((unsigned int) pipe_param->dest.odm_combine*2); in get_surf_rq_param()
1275 if (dst->odm_combine) { in dml_rq_dlg_get_dlg_params()
1305 if (dst->odm_combine == dm_odm_combine_mode_disabled) { in dml_rq_dlg_get_dlg_params()
1308 …unsigned int odm_combine_factor = (dst->odm_combine == dm_odm_combine_mode_2to1 ? 2 : 4); // TOD… in dml_rq_dlg_get_dlg_params()
1453 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml_rq_dlg_get_dlg_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20.c | 121 bool odm_combine, in get_refcyc_per_delivery() argument
132 if (odm_combine) in get_refcyc_per_delivery()
1211 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml20_rq_dlg_get_dlg_params()
1224 dst->odm_combine, in dml20_rq_dlg_get_dlg_params()
1235 dst->odm_combine, in dml20_rq_dlg_get_dlg_params()
1260 dst->odm_combine, in dml20_rq_dlg_get_dlg_params()
1271 dst->odm_combine, in dml20_rq_dlg_get_dlg_params()
1299 dst->odm_combine, in dml20_rq_dlg_get_dlg_params()
1309 dst->odm_combine, in dml20_rq_dlg_get_dlg_params()
1331 dst->odm_combine, in dml20_rq_dlg_get_dlg_params()
[all …]
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| D | display_rq_dlg_calc_20v2.c | 121 bool odm_combine, in get_refcyc_per_delivery() argument
132 if (odm_combine) in get_refcyc_per_delivery()
1212 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml20v2_rq_dlg_get_dlg_params()
1225 dst->odm_combine, in dml20v2_rq_dlg_get_dlg_params()
1236 dst->odm_combine, in dml20v2_rq_dlg_get_dlg_params()
1261 dst->odm_combine, in dml20v2_rq_dlg_get_dlg_params()
1272 dst->odm_combine, in dml20v2_rq_dlg_get_dlg_params()
1300 dst->odm_combine, in dml20v2_rq_dlg_get_dlg_params()
1310 dst->odm_combine, in dml20v2_rq_dlg_get_dlg_params()
1332 dst->odm_combine, in dml20v2_rq_dlg_get_dlg_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 97 bool odm_combine, in get_refcyc_per_delivery() argument
108 if (odm_combine) in get_refcyc_per_delivery()
720 if (pipe_param->dest.odm_combine) { in get_surf_rq_param()
1263 if (dst->full_recout_width == 0 && !dst->odm_combine) { in dml_rq_dlg_get_dlg_params()
1278 dst->odm_combine, in dml_rq_dlg_get_dlg_params()
1290 dst->odm_combine, in dml_rq_dlg_get_dlg_params()
1317 dst->odm_combine, in dml_rq_dlg_get_dlg_params()
1329 dst->odm_combine, in dml_rq_dlg_get_dlg_params()
1360 dst->odm_combine, in dml_rq_dlg_get_dlg_params()
1371 dst->odm_combine, in dml_rq_dlg_get_dlg_params()
[all …]
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| /drivers/gpu/drm/amd/display/dc/virtual/ |
| D | virtual_stream_encoder.c | 88 bool odm_combine) in virtual_enc_dp_set_odm_combine() argument
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_stream_encoder.c | 529 bool odm_combine) in enc2_dp_set_odm_combine() argument
533 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); in enc2_dp_set_odm_combine()
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| D | dcn20_resource.c | 2096 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2100 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_4to1;
2104 pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2227 …pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_…
2256 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2261 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1) {
2273 || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2313 if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2316 else if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_4to1)
2975 pipes[pipe_cnt].pipe.dest.odm_combine =
[all …]
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | stream_encoder.h | 241 bool odm_combine);
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| /drivers/gpu/drm/amd/display/dc/dcn30/ |
| D | dcn30_dio_stream_encoder.c | 479 bool odm_combine) in enc3_dp_set_odm_combine() argument
483 REG_UPDATE(DP_PIXEL_FORMAT, DP_PIXEL_COMBINE, odm_combine); in enc3_dp_set_odm_combine()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | display_mode_structs.h | 352 unsigned int odm_combine; member
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| D | display_mode_lib.c | 208 dml_print("DML PARAMS: odm_combine = %d\n", pipe_dest->odm_combine); in dml_log_pipe_params()
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| D | display_mode_vba.c | 449 dst->odm_combine; in fetch_pipe_params()
594 if (dst->odm_combine && !src->is_hsplit) in fetch_pipe_params()
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| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_resource.c | 1114 pipes[pipe_cnt].pipe.dest.odm_combine = in dcn21_calculate_wm()
1117 pipes[pipe_cnt].pipe.dest.odm_combine = 0; in dcn21_calculate_wm()
1123 pipes[pipe_cnt].pipe.dest.odm_combine = in dcn21_calculate_wm()
1126 pipes[pipe_cnt].pipe.dest.odm_combine = 0; in dcn21_calculate_wm()
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