Searched refs:umc_inst (Results 1 – 3 of 3) sorted by relevance
/drivers/gpu/drm/amd/amdgpu/ |
D | umc_v8_7.c | 43 uint32_t umc_inst, in get_umc_8_reg_offset() argument 46 return adev->umc.channel_offs*ch_inst + UMC_8_INST_DIST*umc_inst; in get_umc_8_reg_offset() 89 uint32_t umc_inst = 0; in umc_v8_7_clear_error_count() local 93 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { in umc_v8_7_clear_error_count() 95 umc_inst, in umc_v8_7_clear_error_count() 175 uint32_t umc_inst = 0; in umc_v8_7_query_ras_error_count() local 179 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { in umc_v8_7_query_ras_error_count() 181 umc_inst, in umc_v8_7_query_ras_error_count() 199 uint32_t umc_inst) in umc_v8_7_query_error_address() argument 204 …uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst… in umc_v8_7_query_error_address() [all …]
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D | umc_v6_1.c | 87 uint32_t umc_inst, in get_umc_6_reg_offset() argument 90 return adev->umc.channel_offs*ch_inst + UMC_6_INST_DIST*umc_inst; in get_umc_6_reg_offset() 146 uint32_t umc_inst = 0; in umc_v6_1_clear_error_count() local 155 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { in umc_v6_1_clear_error_count() 157 umc_inst, in umc_v6_1_clear_error_count() 258 uint32_t umc_inst = 0; in umc_v6_1_query_ras_error_count() local 271 LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) { in umc_v6_1_query_ras_error_count() 273 umc_inst, in umc_v6_1_query_ras_error_count() 298 uint32_t umc_inst) in umc_v6_1_query_error_address() argument 303 …uint32_t channel_index = adev->umc.channel_idx_tbl[umc_inst * adev->umc.channel_inst_num + ch_inst… in umc_v6_1_query_error_address() [all …]
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D | amdgpu_umc.h | 39 #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst… argument 41 #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst… argument
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