Lines Matching refs:u32
50 #define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
61 #define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
66 #define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
67 #define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
68 #define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
69 #define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
70 #define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
71 #define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
74 #define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
79 #define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
80 #define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
81 #define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
82 #define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
83 #define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
84 #define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
85 #define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
86 #define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
87 #define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
88 #define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
89 #define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
90 #define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
91 #define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
92 #define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
93 #define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
94 #define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
95 #define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
96 #define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
97 #define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
98 #define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
99 #define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
100 #define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
101 #define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
102 #define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
110 #define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
111 #define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
121 #define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
122 #define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
123 #define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
124 #define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
125 #define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
126 #define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
127 #define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
128 #define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
129 #define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
130 #define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
131 #define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
132 #define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
133 #define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
134 #define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
135 #define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
136 #define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
137 #define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
138 #define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
139 #define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
140 #define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
141 #define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
149 #define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
150 #define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
151 #define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
152 #define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
153 #define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
154 #define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
155 #define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
156 #define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
157 #define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
158 #define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
159 #define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
160 #define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
161 #define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
162 #define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
163 #define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
164 #define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
165 #define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
168 #define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
169 #define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
170 #define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
171 #define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
173 #define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
176 #define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
177 #define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
178 #define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
179 #define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
180 #define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
181 #define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
182 #define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
183 #define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
201 #define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
202 #define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
203 #define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
204 #define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
205 #define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
206 #define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
207 #define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
208 #define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
209 #define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
210 #define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
232 static inline u32 read_tmr0(void) in read_tmr0()
234 u32 val; in read_tmr0()
239 static inline void write_tmr0(u32 val) in write_tmr0()
244 static inline void write_tmr1(u32 val) in write_tmr1()
249 static inline u32 read_tcr0(void) in read_tcr0()
251 u32 val; in read_tcr0()
256 static inline void write_tcr0(u32 val) in write_tcr0()
261 static inline u32 read_tcr1(void) in read_tcr1()
263 u32 val; in read_tcr1()
268 static inline void write_tcr1(u32 val) in write_tcr1()
273 static inline void write_trr0(u32 val) in write_trr0()
278 static inline void write_trr1(u32 val) in write_trr1()
283 static inline void write_tisr(u32 val) in write_tisr()
288 static inline u32 read_wdtcr(void) in read_wdtcr()
290 u32 val; in read_wdtcr()
294 static inline void write_wdtcr(u32 val) in write_wdtcr()
305 static inline u32 read_rcsr(void) in read_rcsr()
309 static inline void write_wdtsr(u32 val) in write_wdtsr()