Lines Matching refs:mcr
91 1: mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
93 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
95 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
97 mcr p15, 0, \rd, c7, c2, 5 @ allocate D cache line
118 mcr p15, 0, r1, c1, c0, 1
128 mcr p15, 0, r0, c1, c0, 0 @ disable caches
147 mcr p15, 0, r1, c10, c4, 1 @ unlock I-TLB
148 mcr p15, 0, r1, c8, c5, 0 @ invalidate I-TLB
154 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
156 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches & BTB
157 mcr p15, 0, r1, c1, c0, 0 @ ctrl register
160 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
179 mcr p14, 0, r0, c7, c0, 0 @ Go to IDLE
191 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
238 mcr p15, 0, r0, c7, c10, 1 @ Clean D cache line
239 mcr p15, 0, r0, c7, c6, 1 @ Invalidate D cache line
263 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
268 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
269 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
284 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
285 mcr p15, 0, r0, c7, c5, 1 @ Invalidate I cache entry
290 mcr p15, 0, r0, c7, c5, 6 @ Invalidate BTB
291 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
305 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
306 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
311 mcr p15, 0, r0, c7, c5, 0 @ Invalidate I cache & BTB
312 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
332 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
336 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
349 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
353 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
366 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
367 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
371 mcr p15, 0, r0, c7, c10, 4 @ Drain Write (& Fill) Buffer
455 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
473 mcr p15, 0, ip, c7, c5, 0 @ Invalidate I cache & BTB
474 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
475 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
476 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
546 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
547 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
548 mcr p14, 0, r4, c6, c0, 0 @ clock configuration, turbo mode.
549 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
550 mcr p15, 0, r6, c13, c0, 0 @ PID
551 mcr p15, 0, r7, c3, c0, 0 @ domain ID
552 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
553 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
561 mcr p15, 0, ip, c7, c7, 0 @ invalidate I, D caches & BTB
562 mcr p15, 0, ip, c7, c10, 4 @ Drain Write (& Fill) Buffer
563 mcr p15, 0, ip, c8, c7, 0 @ invalidate I, D TLBs
566 mcr p15, 0, r0, c15, c1, 0 @ affects USR or SVC modes